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Patent # Description
US-7,450,358 ESD protective circuit for an electronic circuit having two or more supply voltages
The ESD protective circuit according to the invention is designed for an electronic circuit which uses at least one first and one second supply voltage. This ESD...
US-7,449,925 Method for initialization of electronic circuit units, and electric circuit
In a method for initializing at least one electronic circuit unit of an electric circuit, a supply voltage is applied to a power supply connection unit of the...
US-7,449,909 System and method for testing one or more dies on a semiconductor wafer
A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The...
US-7,449,903 Method and system for the optical inspection of contact faces at semiconductor devices with different appearances
A system and method is provided that reliably determines the position of contact needle tips on a contact pad irrespective of the contact pad geometry and the...
US-7,449,801 Semiconductor circuit arrangement for controlling a high voltage or a current of high current intensity
In the case of a semiconductor circuit arrangement for controlling a high voltage with a series circuit of semiconductor modules, the high voltage possibly being...
US-7,449,778 Power semiconductor module as H-bridge circuit and method for producing the same
A power semiconductor module (41) as H-bridge circuit (42) has four power semiconductor chips (N1, N2, P1, P2) and a semiconductor control chip (IC). The...
US-7,449,777 Circuit arrangement comprising a power component and a drive circuit integrated in two semiconductor bodies
A circuit arrangement comprises at least one power component and a drive circuit for the power component, which are integrated in a first and a second...
US-7,449,739 Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor
A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor...
US-7,449,409 Barrier layer for conductive features
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating...
US-7,449,389 Method for fabricating a semiconductor structure
A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first...
US-7,449,374 Methods of manufacturing semiconductor devices with rotated substrates
Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred...
US-7,448,797 Component arrangement and method for determining the temperature in a semiconductor component
A component arrangement is disclosed herein comprising a temperature sensor integrated in a semiconductor body, said temperature sensor being designed to...
US-7,447,880 Processor with internal memory configuration
A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory...
US-7,447,805 Buffer chip and method for controlling one or more memory arrangements
A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion...
US-7,447,437 Interface arrangement for opto-electronic data transfer, and plug-in opto-electronic transceiver
An interface arrangement for opto-electronic data transfer which has an electrical plug connection part which includes at least one electrical contact used by a...
US-7,447,053 Memory device and method for operating such a memory device
A memory device and method for operating a memory device is described. In one embodiment, the memory device has at least one memory cell including an active...
US-7,446,605 Amplifier arrangement with controllable gain and method for controlling an amplifier gain
An amplifier arrangement with controllable gain includes a first and a second amplifier device which each have a control input to receive a control signal to...
US-7,446,557 Adjusting driver stage output impedance
In order to generate a control signal for adjusting a driver stage with an adjustable output impedance, an impedance signal is generated for a measure of the...
US-7,446,379 Transistor with dopant-bearing metal in source and drain
A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are...
US-7,446,373 Semiconductor component and method for producing it
A semiconductor component and also a method for producing it are disclosed. In one embodiment, the semiconductor component includes a surface region or a...
US-7,445,985 DRAM memory and method for fabricating a DRAM memory cell
A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench...
US-7,445,963 Semiconductor package having an interfacial adhesive layer
A semiconductor package has a substrate (8) and a semiconductor die (2). The substrate (8) includes a plurality of contact pads (9) on its upper surface and a...
US-7,445,959 Sensor module and method of manufacturing same
The embodiments herein relate to sensor modules having sensor chips with a sensing region on a face thereof, and methods for their manufacture.
US-7,444,488 Method and programmable unit for bit field shifting
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit...
US-7,443,742 Memory arrangement and method for processing data
A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device...
US-7,443,740 Integrated semiconductor memory with adjustable internal voltage
An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to...
US-7,443,713 Integrated semiconductor memory and method for operating a semiconductor memory
An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense...
US-7,443,484 Method for exposing a semiconductor wafer by applying periodic movement to a component
A method of focus variation is described herein to achieve a one-step exposure of a wafer without the limitation of applying a complex y-tilt to a wafer stage....
US-7,443,254 Relaxation oscillator with propagation delay compensation for improving the linearity and maximum frequency
A tunable oscillator comprises a control supply configured to output a control output operable to tune the tunable oscillator. The tunable oscillator further...
US-7,443,247 Circuit arrangement for detection of a locking condition for a phase locked loop, and a method
A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is...
US-7,443,238 Amplifier stage, operational amplifier and method for amplifying a signal
An amplifier stage includes a first and a second signal path having a series connection of a first transistor of a first conduction type which forms a control...
US-7,443,199 Circuit arrangement for voltage selection, and method for operating a circuit arrangement for voltage selection
The circuit arrangement includes a first and a second input to supply a first and a second supply voltage and also an output. The circuit arrangement includes a...
US-7,443,178 Circuit arrangement of the temperature compensation of a measuring resistor structure
An electrical circuit for the temperature compensation of at least one measuring resistor structure integrated in a semiconductor body includes at least one...
US-7,443,019 Semiconductor device with conductor tracks between semiconductor chip and circuit carrier and method for...
The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same....
US-7,443,014 Electronic module and method of assembling the same
An electronic module includes a semiconductor power switch and a semiconductor diode. The lower side of the semiconductor power switch includes an output contact...
US-7,442,756 Polymer for sealing porous materials during chip production
A compound and method for sealing or protecting porous materials used in semiconductor fabrication, and in particular for protecting the inner walls of trenches...
US-7,442,624 Deep alignment marks on edge chips for subsequent alignment of opaque layers
A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of...
US-7,442,609 Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like...
US-7,442,605 Resistively switching memory
The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode...
US-7,442,582 Method for producing a chip-substrate connection
A method and an apparatus for producing a chip-substrate connection by alloying or brazing, using a solder containing two or more components with at least two...
US-7,440,861 Concept of compensating for piezo influences on integrated circuitry
The inventive circuitry on a semiconductor chip includes a first functional element having a first electronic functional-element parameter that exhibits a...
US-7,440,499 Fractional spaced equalizer
Fractional Spaced Equalizer FSEQ having adjustable coefficients ci for equalizing a reception signal of a transceiver. The transceiver comprises an echo...
US-7,440,402 Hybrid DSL system for transmission of hybrid DSL data via a subscriber access line in order to increase the...
The hybrid DSL system (10) for transmission of hybrid DSL data via a subscriber access line (2030) has a baseband transceiver (101) for transmission of first...
US-7,440,334 Multi-transistor memory cells
A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array....
US-7,440,309 Memory having parity error correction
A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word...
US-7,439,824 Bulk acoustic wave filter and method for eliminating unwanted side passbands
A bulk acoustic wave (BAW) filter (40) is fabricated from thin film bulk acoustic wave resonators and a method eliminates unwanted side passbands. This BAW...
US-7,439,765 Mask-programmable logic macro and method for programming a logic macro
A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors...
US-7,439,761 Apparatus and method for controlling a driver strength
Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating...
US-7,439,591 Gate layer diode method and apparatus
Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments...
US-7,439,579 Power semiconductor with functional element guide structure
A trench transistor is described. In one aspect, the trench transistor has a cell array having a plurality of cell array trenches and a plurality of mesa zones...
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