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Patent # Description
US-9,054,711 Frequency divider
This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M...
US-9,054,618 Safety circuit and emergency power supply for gate control circuit
A power supply circuit can be used to provide an alternating-current supply voltage to an electric motor. The power supply circuit is supplied by line power....
US-9,054,515 Current measurement and overcurrent detection
Techniques are described for determining the amount of current flowing through an electrical conductor of an isolation device by measuring the voltage level...
US-9,054,182 Semiconductor device with field electrode and method
A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for...
US-9,054,181 Semiconductor device, integrated circuit and method of manufacturing a semiconductor device
A semiconductor device includes a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode being...
US-9,054,151 Semiconductor device with laterally varying doping concentrations
A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type...
US-9,054,150 Chip edge sealing
The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least...
US-9,054,123 Method for manufacturing a semiconductor device
A method for producing a semiconductor device is provided. The method includes: providing a wafer including an upper surface and a plurality of semiconductor...
US-9,054,063 High power single-die semiconductor package
A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a...
US-9,054,040 Multi-die package with separate inter-die interconnects
A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a...
US-9,054,035 Increasing the doping efficiency during proton irradiation
A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the...
US-9,048,838 Switching circuit
In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in...
US-9,048,338 Device including two power semiconductor chips and manufacturing thereof
A device includes a first power semiconductor chip having a first face and a second face opposite to the first face with a first contact pad arranged on the...
US-9,048,303 Group III-nitride-based enhancement mode transistor
A Group III-nitride-based enhancement mode transistor includes a heterojunction fin structure. Side faces and a top face of the heterojunction fin structure are...
US-9,048,248 Integrated circuit package assembly including wave guide
Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a...
US-9,048,244 Method for manufacturing a marked single-crystalline substrate and semiconductor device with marking
A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the...
US-9,048,150 Testing of semiconductor components and circuit layouts therefor
In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device...
US-9,048,096 Diode-based ESD concept for DEMOS protection
The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection....
US-9,048,095 Method for manufacturing a semiconductor device having a channel region in a trench
A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a...
US-9,048,091 Method and substrate for thick III-N epitaxy
A method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away...
US-9,048,019 Semiconductor structure including guard ring
One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer...
US-9,047,985 Apparatus, storage device, switch and methods, which include microstructures extending from a support
An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality...
US-9,042,860 Monolithically integrated circuit
A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor....
US-9,042,127 LED power supply
A method can be used for controlling the switching operation of a switching power converter that includes a semiconductor switch coupled in series to an...
US-9,041,505 System and method for a coreless transformer
In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a...
US-9,041,460 Packaged power transistors and power packages
A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control...
US-9,041,433 System and method for driving transistors
In accordance with an embodiment, a circuit includes a first transistor, a second transistor having a reference node coupled to an output node of the first...
US-9,041,375 High resolution control for a multimode SMPS converter and high resolution slope generator
In various embodiments a controller for controlling the operation of a switched mode power supply is provided, the controller comprising: a first signal source...
US-9,041,244 On-board power supply protection
The system includes a first and a second power supply terminal configured to have at least one of a battery and a generator connected thereto, a first external...
US-9,041,226 Chip arrangement and a method of manufacturing a chip arrangement
In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may...
US-9,041,196 Semiconductor module arrangement and method for producing and operating a semiconductor module arrangement
A semiconductor module arrangement includes a semiconductor module having a top side, an underside opposite the top side, and a plurality of electrical...
US-9,041,184 Chip-housing module and a method for forming a chip-housing module
A chip-housing module is provided, the chip-housing module including a carrier configured to carry one or more chips; the carrier including a first plurality of...
US-9,041,170 Multi-level semiconductor package
A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a...
US-9,041,162 Wafer and a method of dicing a wafer
A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
US-9,041,120 Power MOS transistor with integrated gate-resistor
A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor...
US-9,041,084 Memory device and method for making same
Embodiments relate to a method of forming a memory array, comprising: forming a collector layer; forming a plurality of collector regions in the collector...
US-9,041,066 Protection device for normally-on and normally-off high electron mobility transistors
A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound...
US-9,040,389 Singulation processes
In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed...
US-9,040,375 Method for processing a carrier, method for fabricating a charge storage memory cell, method for processing a...
A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two...
US-9,040,354 Chip comprising a fill structure
A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the...
US-9,040,346 Semiconductor package and methods of formation thereof
In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on...
US-9,036,657 Variable load driver with power message transfer
Representative implementations of devices and techniques provide a modulation arrangement for a control signal. The control signal is received as a digital...
US-9,035,690 Circuit arrangement with a first semiconductor device and with a plurality of second semiconductor devices
A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device...
US-9,035,687 Gate clamping
A circuit is described that includes a switch, a switchable clamping element coupled to the switch, and a driver configured to control the switch based at least...
US-9,035,437 Packaged device comprising non-integer lead pitches and method of manufacturing the same
Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device...
US-9,035,375 Field-effect device and manufacturing method thereof
Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region,...
US-9,035,355 Multi-channel HEMT
A transistor device includes a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional...
US-9,035,322 Silicon carbide device and a method for manufacturing a silicon carbide device
A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination...
US-9,034,751 Method for mounting a semiconductor chip on a carrier
A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the...
US-9,034,233 Method of processing a substrate
In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, imprint material may be deposited at least into...
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