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Patent # Description
US-9,171,804 Method for fabricating an electronic component
A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a...
US-9,171,787 Packaged semiconductor device having an embedded system
Disclosed is a packaged device, comprising a carrier comprising a first carrier contact, a first electrical component having a first top surface and a first...
US-9,171,777 Semiconductor device and method for manufacturing a semiconductor device
A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a...
US-9,171,766 Lead frame strips with support members
A lead frame strip includes a plurality of connected unit lead frames. Each unit lead frame has a die paddle for attaching to a semiconductor die, a tie bar...
US-9,171,738 Systems and methods for integrating bootstrap circuit elements in power transistors and other devices
Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments,...
US-9,171,728 Method for forming a power semiconductor device
A method for forming a semiconductor device includes providing a semiconductor body which has a main surface and a first n-type semiconductor region, forming a...
US-9,171,726 Low noise semiconductor devices
Semiconductor devices may be configured to reduce noise in the devices. For example, a semiconductor device may be configured or made with a first doped region...
US-9,171,245 Chip arrangement, analysis apparatus, receiving container, and receiving container system
In various embodiments, a chip arrangement includes a first chip having a first antenna which is monolithically integrated in the first chip and is intended to...
US-9,170,309 Through bias pole for IGMR speed sensing
One embodiment relates to a sensing system that includes a magnetic encoder wheel having alternating pole magnetic domains along a circumference thereof. The...
US-9,170,307 Hall sensors and sensing methods
Embodiments relate to multi-terminal sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can...
US-9,166,706 System and method for testing a radio frequency integrated circuit
In an embodiment, a method of testing a radio frequency integrated circuit (RFIC) includes generating high frequency test signals using the on-chip test...
US-9,166,640 Adjustable impedance matching network
An adjustable impedance matching network includes a first terminal, a second terminal, a reference potential terminal, a transmission line transformer with a...
US-9,166,604 Timing monitor for PLL
Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count...
US-9,166,039 Lateral transistor component and method for producing same
A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in...
US-9,166,028 Circuit configured to adjust the activation state of transistors based on load conditions
Disclosed is a circuit arrangement, including a transistor component with a gate terminal, a control terminal, and a load path between a source and a drain...
US-9,166,027 IGBT with reduced feedback capacitance
An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body...
US-9,166,005 Semiconductor device with charge compensation structure
A semiconductor device is provided. The semiconductor device includes a semiconductor body having a main surface. In a vertical cross-section which is...
US-9,166,000 Power semiconductor device with an edge termination region
A power semiconductor device includes a semiconductor substrate, an active device region disposed in the semiconductor substrate, an edge termination region...
US-9,165,921 Transistor cell array including semiconductor diode
One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of...
US-9,165,895 Method for separating a plurality of dies and a processing device for separating a plurality of dies
A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality...
US-9,165,889 Alignment mark definer
An alignment mark definer is configured to provide a geometrical definition for an actual alignment structure to be formed at a temporary surface of a substrate...
US-9,165,847 Semiconductor device including a material to absorb thermal energy
A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly...
US-9,165,828 Semiconductor device comprising a fuse structure and a method for manufacturing such semiconductor device
A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the...
US-9,165,821 Method for providing a self-aligned pad protection in a semiconductor device
According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over...
US-9,165,792 Integrated circuit, a chip package and a method for manufacturing an integrated circuit
An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area...
US-9,165,162 Processor arrangements and a method for transmitting a data bit sequence
A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a...
US-9,164,868 Multi-tier trace
The disclosure relates to methods and systems for trace solutions in a computer processing system. More specifically, the disclosure relates to methods and...
US-9,164,157 Magnetoresistive device and method for manufacturing the same
A magnetoresistive device includes a carrier, an xMR-sensor, a magnetic layer formed above an active xMR-region of the xMR-sensor and an insulating layer...
US-9,164,156 Apparatus having a back-bias magnet and a semiconductor chip element
An apparatus may include a back-bias magnet; and a semiconductor chip element; wherein the semiconductor chip element has a sensor for measuring a magnetic...
US-9,164,155 Systems and methods for offset reduction in sensor devices and systems
Embodiments relate to systems and methods for reducing errors in sensor devices and systems. In embodiments, the sensor devices comprise magnetic field sensor...
US-9,162,868 MEMS device
A MEMS device includes a fixed electrode and a movable electrode arranged isolated and spaced from the fixed electrode by a distance. The movable electrode is...
US-9,162,615 Direction indicator circuit for controlling a direction indicator in a vehicle
A direction indicator circuit for controlling a direction indicator may include: a first terminal for connecting to a supply voltage terminal; a second terminal...
US-9,160,559 System and method to address devices connected to a bus system
A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is...
US-9,160,165 Semiconductor device including short-circuit protection
A semiconductor device includes a load current path operable to carry a load current from a supply terminal having a supply voltage to an output circuit node....
US-9,159,830 Field effect transistor
In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region...
US-9,159,819 Semiconductor device and RC-IGBT with zones directly adjoining a rear side electrode
A semiconductor device includes a drift zone of a first conductivity type in a semiconductor body. Controllable cells are configured to form a conductive...
US-9,159,796 Method for protecting a semiconductor device against degradation and a method for manufacturing a semiconductor...
A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor...
US-9,159,783 Semiconductor device and substrate with chalcogen doped region
A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides...
US-9,159,777 Die arrangements containing an inductor coil and methods of manufacturing a die arrangement containing an...
In various embodiments, a die arrangement may be provided. The die arrangement may include a die, at least one bond pad, at least one redistribution trace...
US-9,159,720 Semiconductor module with a semiconductor chip and a passive component and method for producing the same
A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side...
US-9,159,719 ESD protection
A two-stage protection device for an electronic component protects against transient disturbances. The electronic component may be a semiconductor component,...
US-9,159,701 Method of manufacturing a chip package, chip package, method of manufacturing a chip assembly and chip assembly
A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first...
US-9,159,698 Method for producing a semiconductor module arrangement
A method for producing a semiconductor module arrangement includes providing a semiconductor module and a printed circuit board. The semiconductor module has a...
US-9,159,669 Nanotube structure based metal damascene process
In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups...
US-9,159,620 Semiconductor structure and method for making same
One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the...
US-9,158,325 Cable quality detection and power consumer devices
In one embodiment, a method includes receiving power at a power consumer device coupled to a power provider device by a cable. The received power is supplied at...
US-9,157,939 System and device for determining electric voltages
A method and to a system can be used for measuring electric voltages in batteries with a number of battery cells. A measuring circuit includes at least one...
US-9,153,706 Film-covered open-cavity sensor package
Techniques for covering open-cavity integrated-circuit packages in a batch process are disclosed. In an example method, a plurality of open-cavity packages are...
US-9,153,674 Insulated gate bipolar transistor
A semiconductor device is disclosed. One embodiment provides a cell area and a junction termination area at a first side of a semiconductor zone of a first...
US-9,153,518 Molded semiconductor package with pluggable lead
A semiconductor package includes a semiconductor die having a plurality of terminals, a molding compound encapsulating the semiconductor die, and a pluggable...
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