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Patent # Description
US-9,269,594 High power ceramic on copper package
According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350...
US-9,269,592 Method of manufacturing a semiconductor device
A transistor is formed by forming a ridge including a first ridge portion and a second ridge portion in a semiconductor substrate, the ridge extending along a...
US-9,268,001 Differential perpendicular on-axis angle sensor
Embodiments relate to magnetic field angle sensors, such as on-axis magnetic field angle sensors. In an embodiment, a magnetic field angle sensor comprises a...
US-9,267,972 Integrated galvanically isolated meter devices and methods for making integrated galvanically isolated meter...
An integrated galvanically isolated meter devices and method for making integrated meter devices are disclosed. An embodiment of an integrated meter device...
US-9,267,781 On-axis magnetic field angle sensors, systems and methods
Embodiments relate to magnetic field sensors, such as magnetic field angle sensors with generally on-axis arrangements of sensor elements relative to a rotation...
US-9,266,719 Methods of manufacture MEMS devices
Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a first semiconductive...
US-9,263,619 Semiconductor component and method of triggering avalanche breakdown
A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor...
US-9,263,563 Semiconductor device package
In an embodiment, a semiconductor device package includes a bidirectional switch circuit. The bidirectional switch circuit includes a first semiconductor...
US-9,263,552 MOS-transistor with separated electrodes arranged in a trench
A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and...
US-9,263,545 Method of manufacturing a high breakdown voltage III-nitride device
A method of manufacturing a semiconductor device includes forming a semiconductor body including a compound semiconductor material on a substrate, the compound...
US-9,263,529 Semiconductor device with vertically inhomogeneous heavy metal doping profile
Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first...
US-9,263,443 Semiconductor device including a normally-off transistor and transistor cells of a normally-on GaN HEMT
A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor...
US-9,263,440 Power transistor arrangement and package having the same
Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second...
US-9,263,439 III-nitride switching device with an emulated diode
Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching...
US-9,263,430 Semiconductor ESD device and method of making same
A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity...
US-9,263,428 Diode biased ESD protection device and method
An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically...
US-9,263,425 Semiconductor device including multiple semiconductor chips and a laminate
A semiconductor device includes a laminate, a first semiconductor chip at least partly embedded in the laminate, a second semiconductor chip mounted on a first...
US-9,263,421 Semiconductor device having multiple chips mounted to a carrier
A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first...
US-9,263,419 Lead frame strips with electrical isolation of die paddles
A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead...
US-9,263,384 Programmable devices and methods of manufacture thereof
Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link...
US-9,263,369 Chip arrangement, wafer arrangement and method of manufacturing the same
Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first...
US-9,263,362 Method of forming a ring-shaped metal structure
A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the...
US-9,263,357 Carrier with hollow chamber and support structure therein
According to various embodiments, a carrier may include: a hollow chamber spaced apart from a surface of the carrier; and at least one support structure within...
US-9,263,328 Semiconductor device and method for making same
One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the...
US-9,263,271 Method for processing a semiconductor carrier, a semiconductor chip arrangement and a method for manufacturing...
A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a...
US-9,263,154 Method and device for evaluating a chip manufacturing process
A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing...
US-9,262,576 Method and apparatus for providing a layout defining a structure to be patterned onto a substrate
A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method...
US-9,261,791 Photoresist application
Devices and methods are provided where photoresist is applied on a substrate and at least some regions of the photoresist are dried prior to removing a...
US-9,261,572 Low offset spinning current hall plate and method to operate it
One embodiment of the present invention relates to a method and apparatus for removing the effect of contact resistances for Hall effect device contacts. In one...
US-9,261,415 System and method for temperature sensing
In accordance with an embodiment, a temperature sensor includes a proportional to absolute temperature (PTAT) current generator having a first current output...
US-9,258,385 Method for loading a program module into a network device and network with network devices
A method for loading program modules into programmable network devices of a network comprises loading an ID-generator into each network device for generating a...
US-9,258,110 Phase detector
A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device...
US-9,258,032 System and method for receiving data across an isolation barrier
In one embodiment, a system for communication has a receiver for receiving data from a passive transmitter capacitively coupled to the receiver. The receiver...
US-9,258,005 Sensor system using multiple modes for analog to digital conversion
A device for converting analog to digital is disclosed. The device includes a dual mode converter and a control unit. The dual mode converter has a coarse mode...
US-9,258,000 Combined lock/out-of-lock detector for phase locked loops
A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference...
US-9,257,983 Level shifter utilizing a capacitive isolation barrier
According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to...
US-9,257,724 Reaction chamber arrangement and a method for forming a reaction chamber arrangement
A reaction chamber arrangement is provided, the reaction chamber arrangement including a first chemical reaction chamber; a second chemical reaction chamber; an...
US-9,257,549 Semiconductor field effect power switching device
A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first...
US-9,257,532 Method for forming a semiconductor device with a trench and an isolation
A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation...
US-9,257,523 Avalanche diode having an enhanced defect concentration level and method of making the same
The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the...
US-9,257,512 Semiconductor component with dynamic behavior
One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor...
US-9,257,511 Silicon carbide device and a method for forming a silicon carbide device
A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation...
US-9,257,503 Superjunction semiconductor device and method for producing thereof
A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a...
US-9,257,448 Integrated semiconductor device having an insulating structure and a manufacturing method
An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second...
US-9,257,424 Semiconductor device
A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage...
US-9,257,342 Methods of singulating substrates to form semiconductor devices using dummy material
In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within...
US-9,257,285 Ion source devices and methods
An ion source includes a chamber defining an interior cavity for ionization, an electron beam source at a first end of the interior cavity, an inlet for...
US-9,254,996 Vertical pressure sensitive structure
Embodiments related to pressure sensitive structures are described and depicted.
US-9,253,569 System and method for a cancelation circuit
In accordance with an embodiment, a cancelation circuit includes a current mirror and a low pass filter. The current mirror includes an input terminal...
US-9,252,354 Vertical hall device with highly conductive opposite face node for electrically connecting first and second...
Vertical Hall device with highly conductive node for electrically connecting first and second Hall effect regions. A vertical Hall device comprises a first Hall...
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