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Configuration for voltage buffering in a dynamic memory using CMOS
A configuration for voltage buffering in dynamic memories based on CMOS technology uses the capacitance of a well structure for buffering the amplified word line...
Semiconductor memory having a memory cell array
A semiconductor memory such as, for example, a DRAM (Dynamic Random Access Memory) includes a memory cell array and an addressing periphery. A first memory cell...
Plastic molding compound, composite body, and filler for a plastic molding
An integrated circuit has a lead frame, on which a chip of a semiconductor material is attached by a layer of adhesive. The layer of adhesive has at least one...
Method of fabricating semiconductor components
Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method...
Method for producing a semiconductor memory device with a multiplicity of
A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor...
Method of producing an open form
An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its...
Device and method of changing the noise characteristic in a receiver of a
data transmission system
A device for changing a noise characteristic in a receiver of a data transmission system that contains a noise predictor that is connected to a noise attenuator....
1-out-of-N decoder circuit
A decoder circuit for driving a selected one from a set of N output lines on the basis of an M-bit address and in response to a turn-on signal contains...
An amplifier circuit configuration includes a data line for transmitting a data signal. The data line is connected to a data signal input of an amplifier by way...
Electronic circuit, test-apparatus assembly, and method for outputting a
Electronic circuits test memory matrices that have address inputs, data outputs and a memory matrix. The memory spaces in the memory matrix can be addressed via...
Memory configuration having redundant memory locations and method for
accessing redundant memory locations
A memory configuration is divided into memory blocks and allows a flexible access to redundant memory locations by using both, redundant column lines and...
Resistor cascade for forming electrical reference quantities and
A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.
Compensation component and process for producing the compensation component
A compensation component includes a drift path formed of p-conducting and n-conducting layers which are led around or along a trench. A process for producing the...
Integrated circuit having capacitive elements
An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is...
Power diode structure
The invention relates to a power diode structure having improved dynamic characteristics which comprises a semiconductor body of a first conduction type. A...
MOS-transistor structure with a trench-gate-electrode and a limited
specific turn-on resistance and method for...
MOS transistor structure having a trench gate electrode and a reduced on resistance, and methods for fabricating a MOS transistor structure A MOS transistor structure...
Low leakage, low capacitance isolation material
A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the...
Method of forming a self-aligned antifuse link
An antifuse (e.g., 130) is formed in an integrated circuit through the use of a block mask (e.g., photoresist 120) during in situ antifuse dielectric formation....
System and method for improved throughput of semiconductor wafer processing
A system and method for improved throughput of semiconductor wafer processing. In one aspect, a wafer carrier is provided having a flat zone capable of holding...
MRAM memory with drive logic arrangement
MRAM memory having a memory cell array (2) comprising magnetoresistive memory components (6a, 6b) arranged in at least one memory cell layer above a...
Integrated memory having memory cells with magnetoresistive storage effect
The integrated memory has memory cells with a magnetoresistive storage effect in a memory cell array in the form of a matrix. The memory cells are each connected...
Circuit configuration and method for setting the switching points of a
A circuit configuration for calibrating the switching points of a decision module that is controlled by an analog input signal, in dependence on a direct...
Power controlled input receiver
A power controlled input receiver, in accordance with the present invention, includes a receiver circuit including a first current source and a second current...
Controlling a brushless DC motor
Systems and methods for controlling a polyphase brushless direct current (DC) motor (12) are described. One system includes a meter (14) coupled to a motor...
Electronic device having a multiplicity of contact bumps
The invention relates to an electronic device having a multiplicity of contact bumps and an intermediate support. In this case, the intermediate support connects...
Double pullback method of filling an isolation trench
Disclosed is a method of filling an isolation trench etched through a silicon nitride layer down into a silicon substrate, comprising performing a first pullback...
Process for producing ultra-pure water, and configuration for carrying out
a process of this nature
A process and a configuration for producing ultra-pure water for a semiconductor manufacturing plant containing a plurality of manufacturing units. In a first...
Chemical mechanical polishing of a metal layer using a composite polishing
A method of polishing a wafer is disclosed. The wafer has formed thereon an oxide layer that has at least one via. A metal layer is formed on the oxide layer and...
Configuration and method for determining whether the counter reading of a
counter has reached a predetermined...
A system and a method are characterized in that the method of detection can be configured by varying a size and/or a position of a time slot to be taken into...
Address generator for generating addresses for an on-chip trim circuit
An address generator for generating addresses for an on-chip trim circuit for tuning a reference voltage produced on a semiconductor chip. The address generator...
Configuration for implementing redundancy for a memory chip
The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy...
Integrated memory having memory cells and reference cells, and
corresponding operating method
An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In...
Level-shifting circuitry having "high" output during disable mode
Level-shifting circuitry having a level-shifting section and an enable/disable section. The level-shifting section is responsive to an input logic signal. The...
Method, system and method of using a component for setting the electrical
characteristics of microelectronic...
The electrical characteristic of a microelectronic circuit configuration that has at least one analog electronic unit is set. In a configuration step, by feeding...
The power MOSFET has a semiconductor layer formed on a highly doped semiconductor substrate of a first conductivity type. The semiconductor layer is itself of...
Double gated transistor
A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the...
Method for regenerating semiconductor wafers
A process is described for recycling test wafers used for quality control or damaged wafers used in the context of chip production by regenerative removal of the...
Method for fabricating a field-effect transistor having an
anti-punch-through implantation region
A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation...
Process flow for sacrificial collar with poly mask
A process for forming a sacrificial collar (116) on the top portion of a deep trench (114). A nitride layer (116) is deposited within the trench (114). A...
Method for fabricating an integrated circuit, in particular an antifuse
The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a...
Method of fabricating a micro-technical structure, and micro-technical
The invention relates to a method for fabricating in particular a TMR element for use in a MRAM, wherein a mask is arranged on a substrate and structured in such...
The arrangement has at least two electrooptic transducers (1, 2) with in each case one optically active zone (1a, 2a). Optical connections (12, 14) which are...
Method for producing structures on the surface of a semiconductor wafer
The invention relates to a method for producing structures on the surface of a semiconductor wafer, in which after the generation of a primary layout...
Method for processing a signal containing data symbols
A method for processing signals composed of data symbols that are each separated from one another by a guard interval. Such signals are used for digital...
Circuit configuration for switching over a receiver circuit in particular
in DRAM memories and DRAM memory...
A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a...
Integrated memory having memory cells and buffer capacitors
An integrated memory includes memory cells each having a selector transistor and a storage capacitor. In each memory cell, the storage capacitor is connected to...
Circuit configuration for mixing an input signal and an oscillator signal
with one another
The circuit configuration mixes an input signal with an oscillator signal. A phase splitter with one input and two voltage outputs receives the oscillator signal...
Delay lock loop and update method with limited drift and improved power
A delay lock loop circuit, in accordance with the present invention includes a delay lock loop unit having a power down mode. The delay lock loop unit includes a...
A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a...
Method of testing memory cells with a hysteresis curve
In the method for testing a memory cell, a test voltage is applied to a memory cell and the test voltage is changed, preferably in incremental or decremental...