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Patent # Description
US-6,485,871 Method of producing phase masks in an automated layout generation for integrated circuits
A method of producing phase masks for automatically generating a layout for an integrated circuit includes the step of compacting a layout of an integrated...
US-6,484,307 Method for fabricating and checking structures of electronic circuits in a semiconductor substrate
A method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate. By using two different masks, in two method...
US-6,484,277 Integrated memory having a redundancy function
A memory has coding units that are used for allocating any one of redundant lines at a time to any one of first lines on an address basis. Each coding unit has a...
US-6,483,960 Optomodule and connection configuration
An optomodule has a carrier substrate; wiring applied on a front side of the carrier substrate; contacts configured on a rear side of the carrier substrate and...
US-6,483,768 Current driver configuration for MRAM
A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line...
US-6,483,166 Semiconductor configuration having an optical fuse
The semiconductor configuration has a packing material that is permeable to radiation energy in a given wavelength band. One or more fuses that adjoin the...
US-6,482,716 Uniform recess depth of recessed resist layers in trench structure
A method for forming uniform-depth recesses across areas of different trench density, in accordance with the present invention, includes providing a substrate...
US-6,482,017 EMI-shielding strain relief cable boot and dust cover
EMI-shielding strain relief boots and dust covers and methods of using these boots and dust covers are described. An inventive EMI-shielding strain relief boot...
US-6,481,294 Sensor array for a capacitance measuring fingerprint sensor, and method for producing such a sensor array
A base layer, which is preferably flexible, has first conductor tracks, a first insulation layer, fine structures with first electrodes, second conductor tracks...
US-6,480,128 High-speed sample-and-hold circuit with gain
A sample-and-hold system that includes a first source follower having an input and an output and a second source follower that includes an input connected in...
US-6,480,064 Method and apparatus for an efficient low voltage switchable Gm cell
A switching Gm cell allowing a wide transconductance range with a limited voltage range. The Gm cell includes a plurality of Gm setting devices, the operation of...
US-6,480,055 Decoder element for generating an output signal having three different potentials and an operating method for...
A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a...
US-6,480,044 Semiconductor circuit configuration
A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and...
US-6,480,039 Input buffer of an integrated semiconductor circuit
An integrated semiconductor circuit having a first operating mode and a second operating mode has a plurality of input buffers. At least one of the input buffers...
US-6,480,038 Bipolar comparator
A bipolar comparator with an asymmetric differential amplifier stage is described. The comparator has two transistors, and the control electrodes of which are...
US-6,480,024 Circuit configuration for programming a delay in a signal path
A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path...
US-6,479,871 Electrostatic discharge (ESD) latch-up protective circuit for an integrated circuit
The ESD protective circuit proceeds from a modified lateral pnpn "latch-up" protective structure having a highly doped n-type zone, which is arranged on the well...
US-6,479,396 Dry polymer and oxide veil removal for post etch cleaning
In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical...
US-6,479,373 Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a...
Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by...
US-6,477,106 Circuit configuration for deactivating word lines in a memory matrix
A circuit configuration for deactivating word lines in a memory matrix. The circuit configuration contains controllable connection devices for connecting the...
US-6,477,099 Integrated circuit with a differential amplifier
An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an...
US-6,477,095 Method for reading semiconductor die information in a parallel test and burn-in system
A method according to the present invention is provided for determining memory device identification. The method invokes a serial output from n identification...
US-6,477,081 Integrated memory having memory cells with a magnetoresistive storage property
An integrated memory has memory cells with a magnetoresistive storage property. The memory cells are connected in each case between a column line and a row line....
US-6,477,078 Integrated memory having memory cells that each include a ferroelectric memory transistor
An integrated memory has word lines that run in a first direction, and bit lines and control lines that run in a second direction, which is perpendicular to the...
US-6,476,658 Circuit configuration with protection device
The circuit configuration, in particular a DRAM element, has a protection device for suppressing the formation and/or emission of a reflection signal caused by a...
US-6,476,657 Pulse generator for generating an output in response to a delay time
A pulse generator circuit, in particular for use in or for integrated circuits, which, in the usual way, has a number of inverting elements connected in series,...
US-6,476,650 Method for outputting data and circuit configuration with driver circuit
A method and also a circuit configuration with a driver circuit for the parallel amplification of two input signals is described. A first and a second amplified...
US-6,476,593 Method and circuit for compensation control of offset voltages of a radio receiving circuit integrated in a...
A method and circuit for compensation control of offset voltages of a radio receiving circuit integrated in a circuit module that can be used in receiver and...
US-6,475,919 Method for producing trenches for DRAM cell configurations
The invention relates to a method for producing trenches for manufacturing storage capacitors in DRAM cell configurations. In the method, a two-stage hard mask...
US-6,475,859 Plasma doping for DRAM with deep trenches and hemispherical grains
A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding...
US-6,474,558 Data carrier for operation with and without contacts
A data carrier, in particular a chip card, includes a first logic circuit, a contactless interface circuit, at least one coil in which a signal is induced, a...
US-6,473,872 Address decoding system and method for failure toleration in a memory bank
The present invention discloses a row address decoding system and method for tolerating failures on a pair of wordlines in a memory bank by separately addressing...
US-6,473,335 MRAM configuration
A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two...
US-6,473,324 Layout of a sense amplifier with accelerated signal evaluation
A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in...
US-6,472,892 Configuration for testing chips using a printed circuit board
A configuration for testing chips includes a printed circuit board having conductive probe needles to electrically connect the printed circuit board to chips and...
US-6,472,767 Static random access memory (SRAM)
A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the...
US-6,472,696 Memory cell configuration and corresponding production process
The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in...
US-6,472,301 Method and structure for shallow trench isolation
A method (see e.g., FIG. 4) of fabricating a semiconductor device includes forming a trench 12 in a semiconductor body 10. A dielectric layer 26 is formed within...
US-6,472,291 Planarization process to achieve improved uniformity across semiconductor wafers
A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes...
US-6,472,250 Method for producing a chip module
A method for producing a chip module includes punching a chip carrier to form a chip carrier fixing section and chip carrier contact sections spaced apart from...
US-6,472,130 Solution of tetramethylammonium hydroxide in water and a process for preparing the solution
A solution of tetramethylammonium hydroxide in water comprises a surfactant component and a hydrotropic component. A process for preparing a solution for...
US-6,470,114 Retroreflective conductors for optical fiber interconnects
An optical fiber interconnect is provided having a tetrahedral or corner cube retroreflector. The optical fibers are provided in sufficiently close proximity to...
US-6,469,924 Memory architecture with refresh and sense amplifiers
An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and...
US-6,469,887 Capacitor for semiconductor configuration and method for fabricating a dielectric layer therefor
A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide,...
US-6,469,851 Acquisition signal error estimator
A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample...
US-6,469,571 Charge pump with charge equalization for improved efficiency
A charge pump has two inputs, each for an input clock signal, and an output for the output of a pumped output potential. Two pumping capacitors are connected to...
US-6,469,563 Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals
The circuit configuration compensates runtime and pulse-duty-factor differences of two input signals having approximately equal frequency and phase. For each...
US-6,469,549 Apparatus and method for odd integer signal division
The present invention provides a method and/or circuit for achieving a near 50 percent duty cycle divide-by-odd-integer output of an input reference clock.
US-6,469,392 Conductive lines with reduced pitch
An integrated circuit having conductive lines with non-rectangular shaped cross-sections. The non-rectangular shaped cross-sections facilitate a reduction in...
US-6,469,365 Semiconductor component with a structure for avoiding parallel-path currents and method for fabricating a...
A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type...
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