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Patent # Description
US-6,516,428 On-chip debug system
An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an...
US-6,515,891 Random access memory with hidden bits
A random access memory having a multiplicity of memory cells having logic states that can be changed by a control voltage. At least some of the memory cells...
US-6,515,890 Integrated semiconductor memory having memory cells with a ferroelectric memory property
An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a...
US-6,515,874 Clocked power supply
The integrable control circuit drives a semiconductor switch in a switched-mode power supply. The control circuit has a control unit for producing control pulses...
US-6,515,543 Circuit configuration for controlling nonlinear paths
An electrical circuit is provided for controlling nonlinear paths. A first linearization block and a second linearization block are provided, which may each have...
US-6,515,528 Flip-flop circuit
A flip-flop circuit comprises a master latch circuit (2), which receives an input signal (D), and, connected in series therewith, a slave latch circuit (3), the...
US-6,515,514 Method and circuit configuration for controlling a data driver
A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times...
US-6,515,495 Test structure in an integrated semiconductor
With increasing integration density of integrated circuits, the packing density in test regions (kerf structures) located between the integrated circuits cannot...
US-6,515,374 Contact connection of metal interconnects of an integrated semiconductor chip
An integrated semiconductor chip has at least two metal interconnects of two different metallization planes, which are disposed parallel to one another. The...
US-6,515,373 Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys
In an integrated circuit structure, the improvement comprising a wire bonded Cu-pad with Cu-wire component, wherein the Cu-pad Cu-wire component is characterized...
US-6,515,319 Field-effect-controlled transistor and method for fabricating the transistor
An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface...
US-6,514,780 METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING A PARTICULAR FUNCTIONALITY REQUIRED BY A USER OF THE...
An integrated circuit has first structures that are produced in a plurality of wiring planes using exposure masks and serve for producing a functionality...
US-6,514,663 Bottom resist
A bottom resist for the two-layer technique includes a phenolic base polymer, a thermoactive compound which above a temperature of 100.degree. C. releases a...
US-6,513,990 Coupling sleeve having a shielding plate
A coupling sleeve is described which contains a sleeve body with a passage opening for accommodating a coupling partner on both ends respectively. An ...
US-6,513,140 Method and device for decoding convolutional codes
Convolutional codes are decoded by calculating, for uncoded and coded symbols, a first and/or second item of reliability information (.LAMBDA..sub.u and...
US-6,512,716 Memory device with support for unaligned access
An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single...
US-6,512,713 Electronics amplifier circuit having a switchable input transistor, matrix array of memory cells and matrix...
An electronic amplifier circuit according to the principle of current detection is coupled to a memory cell field and has an input transistor for each respective...
US-6,512,688 Device for evaluating cell resistances in a magnetoresistive memory
A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node,...
US-6,512,404 Low voltage charge pump for use in a phase locked loop
A low voltage charge pump for a phase locked loop is disclosed. The low voltage charge pump provides linear control for a voltage at a loop filter. The charge...
US-6,512,259 Capacitor with high-.epsilon. dielectric or ferroelectric material based on the fin stack principle
A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of...
US-6,512,251 Semiconductor switching element that blocks in both directions
The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and...
US-6,511,918 Method of structuring a metal-containing layer
The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas...
US-6,511,791 Multiple exposure process for formation of dense rectangular arrays
A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the...
US-6,510,514 Device for reliability creating electronic signatures
A device for reliably creating electronic signatures that includes a data carrier read/write device, a data generating device, and a display device. The data...
US-6,510,474 Methods and apparatus for re-reordering command and data packets in order to restore an original order of...
According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests...
US-6,510,079 MRAM configuration
A MRAM configuration in which the word lines have a low-resistance connection to the programming lines and the sources of the select transistors can be connected...
US-6,509,849 Method and device for digitally coding binary data with a particular transmit signal spectrum
A coding device for coding binary data with a particular transmit signal spectrum, the coding device having a data stream separating device for separating a data...
US-6,509,792 Circuit and method for attenuating or eliminating undesired properties of an operational amplifier
A compensation circuit for attenuating or eliminating undesired properties of an operational amplifier and a corresponding compensation method determine...
US-6,509,770 Charge pump and PLL
A charge pump has a reference stage that simulates the output stage of the paths, at least in terms of the output-side transistors of the paths. An equivalent...
US-6,509,624 Semiconductor fuses and antifuses in vertical DRAMS
A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor...
US-6,509,226 Process for protecting array top oxide
Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET...
US-6,509,208 Method for forming structures on a wafer
A method for fabricating a structure on an integrated circuit wafer, includes applying an anti-sticking coating to a surface of a mold, depositing a first...
US-6,508,970 Liquid transfer molding system for encapsulating semiconductor integrated circuits
An encapsulation system is used to encapsulate semiconductor products. A bottom mold unit includes a mold pot and a mold piston. A substrate loader loads a...
US-6,507,899 Interface for a memory unit
An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal...
US-6,507,528 Circuit configuration for generating sense amplifier control signals
A circuit configuration for generating sense amplifier control signals for a DRAM. The circuit configuration includes, in addition to thin oxide transistors that...
US-6,507,512 Circuit configuration and method for accelerating aging in an MRAM
A circuit configuration and a method for accelerating aging in an MRAM, in which additional circuit are provided in order to feed a higher current into a control...
US-6,507,298 Method for selecting, prioritizing, and A/D conversion of analog signals, and A/D converter configuration that...
A method for A/D conversion of analog signals using an A/D converter, and to an appropriate A/D converter circuit. In order to process converter request signals...
US-6,507,106 Semiconductor module with a number of semiconductor chips and a conductive connection between the semiconductor...
A semiconductor module of the type having a number of semiconductor chips disposed on a chip carrier has at least a second subset of the semiconductor chips...
US-6,506,631 Method for manufacturing integrated circuits and semiconductor wafer which has integrated circuits
A method for manufacturing integrated circuits is described. A semiconductor wafer having an active side with circuit structures is provided. An electrically...
US-6,506,306 Method and an apparatus for treating wastewater from a chemical-mechanical polishing process used in chip...
Wastewater from a chemical-mechanical polishing process (CMP) used in semiconductor chip fabrication has hitherto been, and is still being, discharged into the...
US-6,505,314 Method and apparatus for processing defect addresses
A method and apparatus for processing defect addresses includes a reduced number of defect addresses to the extent necessary for later evaluation of the defect...
US-6,504,751 Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a...
An integrated memory has memory cells with a magnetoresistive storage property. The memory cells are connected in each case between column lines and row lines....
US-6,504,747 Integrated memory with plate line segments
The integrated memory has driver units DRVi, via which the column select lines CSLi are connected to the plate line segments PLi and which, as a function of the...
US-6,504,434 Method for configuring low-noise integrated amplifier circuits
A method for configuring low-noise integrated amplifier circuits having an input stage with a transistor includes noise matching the circuit to the real part of...
US-6,504,397 Output controlled line driver with programmable common mode control
A differential line driver having integrated output termination resistors is disclosed. The termination resistors are a combination of a controlled transistor...
US-6,504,394 Configuration for trimming reference voltages in semiconductor chips, in particular semiconductor memories
A circuit configuration for trimming reference voltages in semiconductor chips. The circuit configuration contains a test logic unit and a trimming circuit for...
US-6,504,359 Method and device for testing electronic components
A method for testing electronic components includes the step of outputting test output data for the tested electronic components on a test board without...
US-6,504,230 Compensation component and method for fabricating the compensation component
A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a...
US-6,504,200 DRAM cell configuration and fabrication method
Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend...
US-6,503,844 Notched gate configuration for high performance integrated circuits
A notched gate configuration for high performance integrated circuits. The method of producing the notched gate configuration comprises forming a dielectric...
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