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Chip ID register configuration
A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially...
Memory cell configuration
A memory cell configuration has memory cells, each with a trench capacitor in a trench and a vertical transistor, which is used as a selection transistor. The...
Sigma-delta analog-to-digital converter array
A sigma-delta analog-to-digital converter array including two cascaded sigma-delta modulators, the two sigma-delta modulators being multi-bit sigma-delta...
Protection circuit for an integrated circuit
The invention is directed to a protective circuit for an integrated circuit 1. This protective circuit is preferably arranged in a plurality of circuit levels 2,...
Semiconductor chip and a lead frame
A semiconductor chip includes a semiconductor substrate having an electronic circuit theron and a number of bond pads thereon. The bond pads are coupled to the...
Chip crack stop design for semiconductor chips
A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive...
Multi-level fuse structure
A semiconductor device has a first conductor and a second conductor for fuse terminals. A fuse portion is disposed on a different level relative to both the...
Magnetoresistive element and use thereof as a memory element in a memory
In a magnetoresistive element, a non-magnetic layer element is disposed between a first ferromagnetic layer element and a second ferromagnetic layer element. The...
High-voltage semiconductor component, method for the production and use
The invention concerns a semiconductor component with at east one lateral region which is provided to accommodate a lateral electric field strength, whereby the...
Method for fabricating a patterned layer
A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at...
Release mechanism for pluggable fiber optic transceiver
A release mechanism for manually securing a pluggable fiber optic transceiver to a cage mounted on a host circuit board. The transceiver is secured to the cage...
Method of producing masks for fabricating semiconductor structures
Masks are produced for the fabrication of semiconductor structures based on layout data that has information for defining a mask layout with individual geometric...
Method for detecting and classifying scratches occurring during wafer
This method for detecting and classifying a scratch on a semiconductor wafer, in accordance with the invention, first defines a coordinate system on the wafer....
Asynchronous timing for interpolated timing recovery
A zero phase restart circuit (308) estimates a quotient (y.sub.2 -y.sub.0 /(y.sub.3 -Y.sub.1), where y.sub.k are asynchronous samples of a sequence. The quotient...
DRAM memory cell
A DRAM memory cell includes a storage capacitor device with two storage capacitors connected in parallel with one another. One of the storage capacitors is a...
Bidirectional module for multichannel use
A compact bidirectional module for multichannel use includes at least one transmitter and at least one receiver combined in a transmission/reception unit...
Circuit configuration for low-power reference voltage generation
A circuit configuration for low-power reference voltage generation, is described. The circuit has a programmable voltage source which generates an output voltage...
Receiver immune to slope-reversal noise
A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage...
Reference current source having MOS transistors
A reference current source includes at least one first voltage-controlled current source, at least one second voltage-controlled current source, and an addition...
Configuration and method for connecting conductor tracks
A configuration for connecting conductor tracks includes a first conductor track fabricated with a first phase mask having a first phase and a second conductor...
DRAM cell arrangement
A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a...
DRAM including an address space divided into individual blocks having
memory cells activated by row address signals
A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a...
Memory employing multiple enable/disable modes for redundant elements and
testing method using same
A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each...
Serial MRAM device
An MRAM device (100) and method of manufacturing thereof having magnetic memory storage cells or stacks (MS0, MS1, MS2, MS3) coupled together in series. Devices...
Device for evaluating cell resistances in a magnetoresistive memory
A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array...
Method and configuration for compensating for parasitic current losses
A method and a configuration are provided for compensating for parasitic current losses in an MRAM memory cell array. Individual word lines and bit lines are...
Memory cell configuration, magnetic ram, and associative memory
A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are...
Circuit for receiving and driving a clock-signal
A receiver circuit includes a first circuit having two modes of operation controlled by a feedback loop. The feedback loop is connected to an output of the first...
Standby voltage controller and voltage divider in a configuration for
supplying voltages to an electronic circuit
The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with...
Optical semiconductor component with an optically transparent protective
The optical semiconductor component has a semiconductor body having a first surface with an active region and a second surface with a passive region. An...
Elimination/reduction of black silicon in DT etch
In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate "black silicon" comprising: a) providing a...
Method for setting the breakover voltage of a thyristor
The effective doping profile of a finished thyristor is altered with helium ions radiated into a region provided for triggering the thyristor in such a way that...
Optoelectronic coupling element and production method
The optoelectronic coupling element is adjustable, during production, with regard to an optimal light path. A coupling part has a coupling device for coupling...
Opto-electronic assembly having an integrated imaging system
An opto-electronic assembly includes an opto-electronic transducer, an optical path and an imaging system in the form of a translucent hollow body having...
Device for cleaning a wafer of abrasive agent suspension remaining after
polishing with brushes and DI water
A device for cleaning a wafer of abrasive agent suspension (slurry) remaining after polishing with brushes and DI water includes an upper gear casing having an...
Integrated memory having memory cells and reference cells, and operating
method for such a memory
The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the...
Circuit configuration for reading and writing information at a memory cell
Binary information is written to and read from a memory cell field forming a matrix-type field of rows and columns via a plurality of write/read circuits, each...
Magnetoresistive memory and method for reading a magnetoresistive memory
A magnetoresistive memory includes magnetoresistive memory cells disposed in a plurality of rows and/or columns. A bit line is connected to first poles of the...
A magneto-resistive random access memory (MRAM) configuration is described in which a plurality of memory cell blocks are supplied with operating voltages that...
Retention time of memory cells by reducing leakage current
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written...
Offset-free analog-to-digital converter
Analog-to-digital converter for converting an analog input signal which is present at a signal input (2a, 2b) and has a specific frequency bandwidth, into an...
To keep the power consumption in the modulator-demodulator of a mobile radio as low as possible, the modulator-demodulator has a voltage-controlled oscillator....
Compensation circuit for driver circuits
The invention relates to a compensation circuit for driver circuits having a current reference source which generates at least one reference signal which is...
In-situ method for measuring the endpoint of a resist recess etch process
An in-situ method for measuring the endpoint of a resist recess etch process for DRAM trench cell capacitors to determine the buried plate depth on a...
Chip carrier having ventilation channels
A chip carrier made of a non-metallic material has conductor tracks applied thereon for producing an external, two-dimensional connection configuration for...
Crack stop between neighboring fuses for protection from fuse blow damage
A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated...
Semiconductor contact and method of forming the same
In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed...
Method of fabricating semiconductor devices with contact studs formed
without major polishing defects
In a semiconductor device, a contact stud (100) contacts a semiconductor substrate (10); the stud is embedded in an insulating structure with a first insulating...
Integrated circuit trench device with a dielectric collar stack, and method
of forming thereof
A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably...
Low temperature carbon rich oxy-nitride for improved RIE selectivity
Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with...