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Patent # Description
US-6,577,526 Magnetoresistive element and the use thereof as storage element in a storage cell array
The magnetoresistive element has a first ferromagnetic element, a nonmagnetic layer element, and a second ferromagnetic layer element arranged in such a way that...
US-6,577,509 Semiconductor circuit and switch-mode power supply
The invention relates to a semiconductor circuit having a drive circuit, a load that is disposed between a supply voltage, and a controllable, clocked...
US-6,577,196 Method and circuit for automatic gain control of a signal amplifier
Automatic gain control circuit for setting the gain of a signal amplifier having a peak value detector for measuring signal amplitudes of the analogue signal...
US-6,576,995 Housing for semiconductor chips
A housing for semiconductor chips includes a plastic base substrate having a region for accommodating a chip and substrate sides having a patterned metallization...
US-6,576,953 Vertical semiconductor component with source-down design and corresponding fabrication method
The present invention provides a semiconductor component having a substrate (10) of a first conduction type (n.sup.+); provided on the substrate (10), an...
US-6,576,948 Integrated circuit configuration and method for manufacturing it
An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a...
US-6,576,944 Self-aligned nitride pattern for improved process window
A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first...
US-6,576,565 RTCVD process and reactor for improved conformality and step-coverage
An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber...
US-6,576,550 `Via first` dual damascene process for copper metallization
An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The...
US-6,576,150 Process for the production of a glass article having at least one recess
An etching mask with at least one etching window is applied on a glass object consisting substantially of boron silicate glass. Subsequently, the glass object is...
US-6,575,790 Detachable connecting system
A detachable connecting system includes a component and a mount having cooperating guides which effect a defined movement of the component in a mounting...
US-6,574,413 Arrangement and method for the channel-dependent attenuation of the levels of a plurality of optical data channels
The invention relates to an arrangement and a method for the channel-dependent attenuation of the levels of a plurality of optical data channels which each...
US-6,574,390 Configuration to multiplex and/or demultiplex the signals of a plurality of optical data channels and method...
The invention relates to an arrangement for multiplexing and/or demultiplexing the signals of a plurality of optical data channels of different wavelength, in...
US-6,574,291 Turbo-code decoder and turbo-code decoding method with iterative channel parameter estimation
A turbo-code decoder with iterative channel parameter estimation for decoding turbo-coded received data that includes systematic information data and redundant...
US-6,574,155 Redundant multiplexer for a semiconductor memory configuration
A redundant multiplexer, in which the addresses of two series-connected switches are compared, and the switches are possibly interchanged, to ensure that no...
US-6,574,138 Memory cell configuration and method for operating the configuration
A memory cell configuration has memory cells that each contain two magnetoresistive elements. If the two magnetoresistive elements of each memory cell are...
US-6,574,132 Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits
The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the...
US-6,573,796 Automatic LDMOS biasing with long term hot carrier compensation
Disclosed are systems and methods for automatic biasing of LDMOS devices at turn-on. The invention provides bias point setting with compensation for hot carrier...
US-6,573,754 Circuit configuration for enabling a clock signal in a manner dependent on an enable signal
A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The...
US-6,573,593 Integrated circuit with a housing accommodating the integrated circuit
An integrated circuit having a housing accommodating the integrated circuit. It being possible for the integrated circuit to be put optionally into one of a...
US-6,573,561 Vertical MOSFET with asymmetrically graded channel doping
Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are...
US-6,573,542 Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer
The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an...
US-6,573,192 Dual thickness gate oxide fabrication method using plasma surface treatment
A method of forming on a common semiconductor body (substrate) silicon oxide layers of different thicknesses uses plasma treatment on selected portions of an...
US-6,573,145 Process for producing an MOS field effect transistor with a recombination zone
A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination...
US-6,573,136 Isolating a vertical gate contact structure
The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust...
US-6,572,280 Optical transmitting/receiving module including an internal optical waveguide
A module essentially includes a module housing, into which is introduced a lead frame. An electro-optical transducer is mounted on the lead frame. The interior...
US-6,571,383 Semiconductor device fabrication using a photomask designed using modeling and empirical testing
A method of fabricating a semiconductor device is outlined in FIG. 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A...
US-6,571,320 Cache memory for two-dimensional data fields
The cache memory is particularly suitable for processing images. The special configuration of a memory field, an allocation unit, a write queue, and a data...
US-6,570,794 Twisted bit-line compensation for DRAM having redundancy
A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and...
US-6,570,793 Semiconductor memory having a redundancy circuit for word lines and method for operating the memory
A redundancy circuit for a semiconductor memory having word lines and redundant word lines is described. The redundancy circuit activates the word line at the...
US-6,570,512 Circuit configuration for quantization of digital signals and for filtering quantization noise
The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a...
US-6,570,447 Programmable logarithmic gain adjustment for open-loop amplifiers
Transconductance-based variable gain amplifiers amplify an input voltage by converting the voltage difference to a current and then amplifying the result. At...
US-6,570,439 Circuit arrangement to reduce the supply voltage of a circuit part and process for activating a circuit part
In order to achieve reliable operation despite the greater interference susceptibility of a circuit (1) at a reduced power supply, in addition to a global power...
US-6,570,434 Method to improve charge pump reliability, efficiency and size
A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in...
US-6,570,367 Voltage generator with standby operating mode
A voltage generator for producing an internal supply voltage has a standby voltage generator and a voltage generator for normal operation that are controlled in...
US-6,569,772 Method for producing an alternating phase mask
A carrier has a surface with a mask layer thereon. An irradiation-sensitive layer on the mask layer is exposed and developed to form a first exposure structure....
US-6,569,769 Slurry-less chemical-mechanical polishing
The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even...
US-6,568,862 Coupling device for connecting an optical fiber to an optical transmitting or receiving unit and transmitting...
A coupling device is for coupling an optical fiber to an optical transmitting or receiving unit. The coupling device can be included in a transmitting or...
US-6,567,666 Forward link inter-generation soft handoff between 2G and 3G CDMA systems
In a CDMA cellular radiotelephone system, a soft handoff (SHO) is performed when a mobile station communicates with a new inter-generation base station, without...
US-6,567,439 Radio-frequency laser module and a method for producing it
A radio-frequency laser module has a substrate and a semiconductor laser disposed on the substrate. An electrical RF conductive path is provided on the...
US-6,567,300 Narrow contact design for magnetic random access memory (MRAM) arrays
An MRAM device (200) and method of manufacturing thereof having second conductive lines (228) with a narrow width. The second conductive lines (228) partially...
US-6,566,273 Etch selectivity inversion for etching along crystallographic directions in silicon
Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One...
US-6,566,271 Method of producing a semiconductor surface covered with fluorine
Fluorine is deposited on a semiconductor substrate surface according to a novel process. A semiconductor substrate is placed in a reaction chamber and the...
US-6,566,238 Metal wire fuse structure with cavity
An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes...
US-6,566,228 Trench isolation processes using polysilicon-assisted fill
Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the...
US-6,566,227 Strap resistance using selective oxidation to cap DT poly before STI etch
A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a...
US-6,566,220 Method for fabricating a semiconductor memory component
The invention relates to a method for fabricating a semiconductor memory component, in particular a DRAM or FeRAM having a silicon substrate. The lower electrode...
US-6,566,219 Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the...
A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g.,...
US-6,566,193 Method for producing a cell of a semiconductor memory
The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the...
US-6,566,187 DRAM cell system and method for producing same
DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a...
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