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Patent # Description
US-6,542,395 Integrated DRAM memory module
The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are...
US-6,542,389 Voltage pump with switch-on control
The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a...
US-6,542,100 Apparatus and method for filtering a signal which represents a digital data stream
A signal to be produced, which represents a digital data stream, is generated using the currents or voltages from current or voltage sources selected from...
US-6,542,054 Acoustic mirror and method for producing the acoustic mirror
An acoustic mirror is described which is formed of at least one first insulating layer, a first metal layer disposed thereon, a second insulating layer disposed...
US-6,541,999 Circuit configuration with temperature protection and method for implementing the temperature protection
A configuration for protecting an integrated circuit against over-temperature conditions is described. The configuration has at least one detector device, which...
US-6,541,833 Micromechanical component with sealed membrane openings and method of fabricating a micromechanical component
The method for producing a micromechanical component includes the following steps: producing a semi-finished micromechanical component; producing openings and...
US-6,541,818 Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer...
A field effect transistor configuration with a trench gate electrode and a method for producing the same. An additional highly doped layer is provided in the...
US-6,541,804 Junction-isolated lateral MOSFET for high-/low-side switches
The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain...
US-6,541,387 Process for implementation of a hardmask
A resist layer is deposited atop a substrate and is patterned to expose portions of a substrate. A hardmask layer is deposited atop the patterned resist layer...
US-6,541,372 Method for manufacturing a conductor structure for an integrated circuit
A simple to manufacture conductor structure is described which requires only a small number of process steps. The conductor structure contains a structured,...
US-6,541,334 Integrated circuit configuration having at least one buried circuit element and an insulating layer, and a...
The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with...
US-6,541,311 Method of positioning a component mounted on a lead frame in a test socket
A lead frame is configured with conductor leads, a dam bar and an extension between the conductor leads. The extension projects from the dam bar toward a central...
US-6,540,555 Shielding plate, in particular for optoelectronic transceivers
The shielding plate is particularly suited for optoelectronic transceivers. The shielding plate is a hollow body in the form of a casing and has contact springs...
US-6,540,413 Fiber-optic transmitting component with precisely settable input coupling
In a fiber-optic transmitting component, either an adjusting sleeve (3) or a fiber flange is provided with a polarization filter (5) and an adjustment step is...
US-6,539,625 Chromium adhesion layer for copper vias in low-k technology
In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by...
US-6,539,505 Method of testing a semiconductor memory, and semiconductor memory with a test device
In order to test a semiconductor memory, a bit fail map is generated in that a predetermined data value is written to memory cells and subsequently read out and...
US-6,539,440 Methods and apparatus for prediction of the time between two consecutive memory accesses
According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is...
US-6,539,145 Module for multiplexing and/or demultiplexing optical signals
The invention relates to a module for multiplexing and/or demultiplexing optical signals, having at least one wavelength-selective filter for multiplexing or...
US-6,539,091 Apparatus for sidetone damping
An apparatus for sidetone damping can be used in telephones configured for hands-free operation. The apparatus has a reception branch with a speaker and a...
US-6,539,066 Integrable radio receiver circuit for frequency-modulated digital signals
An FM receiver, which contains quadrature downward mixing to a low IF, analog IF polyphase filters in quadrature signal paths and an analog quadrature signal...
US-6,538,950 Integrated memory and corresponding operating method
An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit...
US-6,538,939 Memory employing multiple enable/disable modes for redundant elements and testing method using same
A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each...
US-6,538,913 Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration
The invention relates to a method for operating a ferroelectric memory configuration in the V.sub.DD /2 mode. The memory configuration has a large number of...
US-6,538,895 TSOP memory chip housing configuration
A configuration of at least two TSOP memory chip housings stacked one on another, is described. Each of the TSOP memory chip housings has at least one memory...
US-6,538,273 Ferroelectric transistor and method for fabricating it
A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic...
US-6,538,229 Method for the positionally accurate adjustment and fixing of a microoptical element
The inventor relates to method for the posibility accurate adjustment and fixing of a microoptical element on a carrier. In this case, an optical position...
US-6,537,926 Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication
A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A...
US-6,537,900 Method for patterning a metal or metal silicide layer and a capacitor structure fabricated by the method
In a method for fabricating a high-epsilon dielectric/ferroelectric capacitor, a patterning layer with a central base layer zone and a Si-filled trench laterally...
US-6,537,885 Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is...
US-6,537,870 Method of forming an integrated circuit comprising a self aligned trench
An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., 128,...
US-6,537,836 Semiconductor structures and manufacturing methods
A semiconductor body having an alignment mark comprising a pair of sets of parallel lines disposed on the semiconductor body, the parallel lines in one of the...
US-6,536,959 Coupling configuration for connecting an optical fiber to an optoelectronic component
A coupling configuration for connecting an optical fiber provided with a coupling end face at one end to an optoelectronic element is described. A coupling...
US-6,536,003 Testable read-only memory for data memory redundant logic
The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units....
US-6,535,454 Circuit configuration for an integrated semiconductor memory with column access
A circuit configuration for an integrated semiconductor memory has memory cells which are configured in a matrix-type memory cell array and which are combined to...
US-6,535,262 Display unit for chip cards with folded sheet a method for manufacturing such a display unit
A display unit includes activation or driver electronics disposed on the rear side of a display element. A display unit has a front region with a display...
US-6,535,059 Amplifier circuit
A reference stage is provided in order to compensate for manufacturing tolerances, for example relating to the threshold voltage of a transistor. This reference...
US-6,535,048 Secure asynchronous clock multiplexer
A system and method for clock multiplexing. According to one implementation, a pair of two stage cross-coupled clock gating elements are controlled by a single...
US-6,535,046 Integrated semiconductor circuit with an increased operating voltage
An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity...
US-6,535,044 Clock signal generator
A clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output (41), the clock signal generator (1) having:...
US-6,535,009 Configuration for carrying out burn-in processing operations of semiconductor devices at wafer level
A configuration for carrying out burn-in processing for semiconductor devices at the wafer level. To this end, BIST units are allocated to the individual...
US-6,535,007 Component holder for testing devices and component holder system microlithography
A component holder for testing electronic components having a carrier, at least one component socket arranged on the carrier and having a group of component...
US-6,534,900 Piezoresonator
A thin film piezoresonator, which can be tuned over a wide range of RF frequencies, includes a piezo layer between a first electrode layer and a second electrode...
US-6,534,830 Low impedance VDMOS semiconductor component
A low impedance VDMOS semiconductor component having a planar gate structure is described. The VDMOS semiconductor component contains a semiconductor body of a...
US-6,534,820 Integrated dynamic memory cell having a small area of extent, and a method for its production
An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate...
US-6,534,376 Process flow for sacrificial collar scheme with vertical nitride mask
A process flow for forming a sacrificial collar (132) within a deep trench (113) of a semiconductor memory cell. A nitride liner layer (120) is deposited over a...
US-6,534,369 Field effect transistor and method of fabrication
An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a...
US-6,534,362 Method for fabricating a memory cell configuration
A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming...
US-6,534,345 Method for mounting a semiconductor chip on a carrier layer and device for carrying out the method
In order to mount a semiconductor chip on a carrier layer, consolidated filler material is applied between the semiconductor chip and the carrier layer. The...
US-6,533,470 Single-piece cage for pluggable fiber optic transceiver
A cage for mounting a pluggable fiber optic transceiver onto a host circuit board. The cage is entirely formed from a single blank, which is folded along...
US-6,533,178 Device for contactless transmission of data
A device for a contactless transmission of data includes a data transceiver with an antenna. The impedance of the antenna of the data transceiver is purposely...
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