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Compensation component and method for fabricating the compensation
A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a...
DRAM cell configuration and fabrication method
Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend...
Notched gate configuration for high performance integrated circuits
A notched gate configuration for high performance integrated circuits. The method of producing the notched gate configuration comprises forming a dielectric...
Double gated transistor
A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the...
Liquid transfer molding system for encapsulating semiconductor integrated
An encapsulation system is used to encapsulate semiconductor products. A bottom mold unit includes a mold pot and a mold piston. A substrate loader loads a...
Electronic driver circuit for word lines in a memory matrix, and memory
An electronic driver circuit for word lines in a memory matrix is described. The driver circuit has coded outputs of a driver source, in particular of a...
High speed multiplexer
A high-speed multiplexer that includes a reduced number of components in the pull-up and/or the pull-down circuits operates faster than conventional multiplexers...
Level-shifting circuitry having "low" output during disable mode
Level-shifting circuitry having a level shifting section and an enable/disable section. The level shifting section is responsive to an input logic signal. The...
Circuit configuration for measuring the capacitance of structures in an
A circuit configuration for measuring the capacitance of structures in an integrated circuit having a test structure and a reference structure, includes first...
Fuse configuration for a semiconductor apparatus
A fuse configuration for a semiconductor apparatus is described. The fuse configuration has a semiconductor material disposed underneath the fuse and is made...
Transistors having independently adjustable parameters
The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate...
Method for manufacturing a trench capacitor of a memory cell of a
A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by...
Method for fabricating a ferroelectric memory configuration
The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a...
Low temperature CVD processes for preparing ferroelectric films using Bi
Chemical vapor deposition is used to form a film of Bi oxide, Sr oxide, and Ta oxide on a heated substrate by decomposing the precursors of these oxides at the...
Usage of redundancy data for displaying failure bit maps for semiconductor
A method for displaying failure information for semiconductor devices, in accordance with the present invention, includes testing a semiconductor device with a...
Fast sense amplifier for nonvolatile memories
A sense amplifier for nonvolatile memories includes a first line path (precharging path) having a first transistor and a third transistor connected in series...
Magnetoresistive random access memory (MRAM) cross-point array with reduced
An architecture for a magnetoresistive random access memory (MRAM) storage cell 300 with reduced parasitic effects is presented. An additional runs of metal laid...
Piecewise-linear, non-uniform ADC
A non-uniform analog-to-digital converter (ADC) produces digital output data representing the magnitude of an analog input signal having a non-uniform magnitude...
Digital-to-analog converter with constant bias voltage
Digital-to-analog converters (DACs) are used to convert digital signals to analog signals. DAC's are typically made of transistors, linked in one of several...
Sigma-delta A/D converter
Sigma-delta A/D converter having at least one analog signal input (1, 2) for applying an analog input signal, a subtraction element (3) having a plurality of...
The invention relates to a semiconductor configuration in which electrodes are insulated by a gas-filled or evacuated cavity. The semiconductor configuration...
Negative ion implant mask formation for self-aligned, sublithographic
resolution patterning for single-sided...
A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a...
Transport device for electronic components with an anticontamination
The transport device for electronic components is formed with at least one recess to accommodate an electronic component. In order to protect the component, the...
Yield prediction and statistical process control using predicted defect
related yield loss
In accordance with the present invention, a method, which may be implemented by employing a program storage device, for determining yield loss for a device...
Chip ID register configuration
A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially...
Memory cell configuration
A memory cell configuration has memory cells, each with a trench capacitor in a trench and a vertical transistor, which is used as a selection transistor. The...
Sigma-delta analog-to-digital converter array
A sigma-delta analog-to-digital converter array including two cascaded sigma-delta modulators, the two sigma-delta modulators being multi-bit sigma-delta...
Protection circuit for an integrated circuit
The invention is directed to a protective circuit for an integrated circuit 1. This protective circuit is preferably arranged in a plurality of circuit levels 2,...
Semiconductor chip and a lead frame
A semiconductor chip includes a semiconductor substrate having an electronic circuit theron and a number of bond pads thereon. The bond pads are coupled to the...
Chip crack stop design for semiconductor chips
A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive...
Multi-level fuse structure
A semiconductor device has a first conductor and a second conductor for fuse terminals. A fuse portion is disposed on a different level relative to both the...
Magnetoresistive element and use thereof as a memory element in a memory
In a magnetoresistive element, a non-magnetic layer element is disposed between a first ferromagnetic layer element and a second ferromagnetic layer element. The...
High-voltage semiconductor component, method for the production and use
The invention concerns a semiconductor component with at east one lateral region which is provided to accommodate a lateral electric field strength, whereby the...
Method for fabricating a patterned layer
A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at...
Release mechanism for pluggable fiber optic transceiver
A release mechanism for manually securing a pluggable fiber optic transceiver to a cage mounted on a host circuit board. The transceiver is secured to the cage...
Method of producing masks for fabricating semiconductor structures
Masks are produced for the fabrication of semiconductor structures based on layout data that has information for defining a mask layout with individual geometric...
Method for detecting and classifying scratches occurring during wafer
This method for detecting and classifying a scratch on a semiconductor wafer, in accordance with the invention, first defines a coordinate system on the wafer....
Asynchronous timing for interpolated timing recovery
A zero phase restart circuit (308) estimates a quotient (y.sub.2 -y.sub.0 /(y.sub.3 -Y.sub.1), where y.sub.k are asynchronous samples of a sequence. The quotient...
DRAM memory cell
A DRAM memory cell includes a storage capacitor device with two storage capacitors connected in parallel with one another. One of the storage capacitors is a...
Bidirectional module for multichannel use
A compact bidirectional module for multichannel use includes at least one transmitter and at least one receiver combined in a transmission/reception unit...
Circuit configuration for low-power reference voltage generation
A circuit configuration for low-power reference voltage generation, is described. The circuit has a programmable voltage source which generates an output voltage...
Receiver immune to slope-reversal noise
A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage...
Reference current source having MOS transistors
A reference current source includes at least one first voltage-controlled current source, at least one second voltage-controlled current source, and an addition...
Configuration and method for connecting conductor tracks
A configuration for connecting conductor tracks includes a first conductor track fabricated with a first phase mask having a first phase and a second conductor...
DRAM cell arrangement
A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a...
DRAM including an address space divided into individual blocks having
memory cells activated by row address signals
A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a...
Memory employing multiple enable/disable modes for redundant elements and
testing method using same
A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each...
Serial MRAM device
An MRAM device (100) and method of manufacturing thereof having magnetic memory storage cells or stacks (MS0, MS1, MS2, MS3) coupled together in series. Devices...
Device for evaluating cell resistances in a magnetoresistive memory
A magnetoresistive memory is described and contains a common word line voltage source, bit lines, word lines crossing the bit lines, and a memory cell array...
Method and configuration for compensating for parasitic current losses
A method and a configuration are provided for compensating for parasitic current losses in an MRAM memory cell array. Individual word lines and bit lines are...