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Patent # Description
US-6,587,544 Method for measuring a load impedance
Method for measuring a load impedance (Z.sub.L) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal...
US-6,587,524 Reception method and receiver for mobile radiotelephone applications
In a receiving method for mobile radio applications, a given user data signal and at least one further user data signal located within the same frequency band...
US-6,587,489 Electronic driver circuit for directly modulated semiconductor lasers
An electronic driver circuit for directly modulated semiconductor lasers is described. The drive circuit has a first circuit for generating a constant current...
US-6,587,361 Switched-mode power supply with low switching losses
A method for driving a switch in a switched-mode power supply, in which the switch is connected in series with a primary coil of a transformer and in which a...
US-6,587,292 Magneto-resistive asymmetry compensation loop
A magneto-resistive asymmetry compensation system includes a linearizer (61) interposed in a data path and a control loop (63). The control loop uses signal...
US-6,586,978 Delay locked loop
A delay locked loop has a filter in order to set the delay time of a delay path in a manner dependent on the phase difference of input and output clock signals....
US-6,586,960 Measuring device for testing unpacked chips
A measuring device has a needle-board circuit board carrying a large number of contact-making needles for contacting connecting areas on an IC circuit. The...
US-6,586,919 Voltage-current converter
The invention concerns a voltage-current converter having: a first current mirror containing two transistors that are designed such that under identical drive...
US-6,586,795 DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties
Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the...
US-6,586,348 Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation...
After an SBT layer is precipitated onto a substrate, the SBT layer is structured as a still amorphous layer. Only subsequently is it subjected to a...
US-6,586,308 Method for producing circuit structures on a semiconductor substrate and semiconductor configuration with...
A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit...
US-6,586,305 Method for producing transistors in integrated semiconductor circuits
Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel...
US-6,586,300 Spacer assisted trench top isolation for vertical DRAM's
A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133)...
US-6,584,681 Method for producing a microelectronic component of sandwich construction
A method for producing a microelectronic component of sandwich construction, which includes the steps of providing a first substrate which has a first conductor...
US-6,584,087 Power control during inter-generation soft handoffs
A method for power control during soft handoffs is disclosed for a multi-user CDMA system having mixed system types, such as IS-95A/B and IS-2000. The procedure...
US-6,584,021 Semiconductor memory having a delay locked loop
A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output...
US-6,584,009 Memory integrated circuit with improved reliability
A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first...
US-6,584,006 MRAM bit line word line architecture
A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the ...
US-6,583,737 Device and method for compensating for propagation delay
The device and method compensate for propagation differences between n serial data streams each transmitted over parallel optical lines. Data that can be...
US-6,583,673 Stability enhanced multistage power amplifier
A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage...
US-6,583,660 Active auto zero circuit for time continuous open loop amplifiers
An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal...
US-6,583,508 Integrated circuit with active regions having varying contact arrangements
The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S1, D1, S2, D2, S3) arranged in parallel next to one...
US-6,583,464 Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor...
A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a...
US-6,583,020 Method for fabricating a trench isolation for electrically active components
A method for fabricating a trench isolation for electrically active components in a semiconductor component. A mask is applied to a semiconductor substrate....
US-6,581,842 Data carrier with regulation of the power consumption
A data carrier, in particular a smart card, is described and has at least one transmitting/receiving antenna and also a rectifier circuit connected downstream...
US-6,581,171 Circuit configuration for the burn-in test of a semiconductor module
A circuit for the burn-in test of a semiconductor module, to which burn-in test signals from a burn-in test device can be applied, has memory elements. Each...
US-6,581,026 Method and configuration for comparing a first characteristic with predetermined characteristics of a technical...
The objective of the invention is to detect a characteristic in a technical system with reference to model checking. A comparison is made, involving the...
US-6,580,960 System and method for finding an operation/tool combination that causes integrated failure in a semiconductor...
A system and method for finding operation/tool's combination which causes the integration failure in a semiconductor fabrication facility is disclosed. It...
US-6,580,903 Circuit and method for recording and playing back voice and other sounds in digital mobile radio devices
A circuit for recording and playing back voice in digital mobile radio devices and a method for appropriately recording and playing back the voice. The circuit...
US-6,580,865 Optical fiber systems
An optical fiber system that enables direct board-to-board optical communication is described. The optical fiber system does not require data transmission...
US-6,580,831 Compression of optical readout biomolecular sensory data
The present invention provides a system and method for compression of image data while preserving the usable information and eliminating or reducing associated...
US-6,580,655 Pre-charge circuit and method for memory devices with shared sense amplifiers
A pre-charge circuit for a memory device having a sense amplifier shared between right and left banks of memory cells and a method of pre-charging the shared...
US-6,580,636 Magnetoresistive memory with a low current density
The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is...
US-6,580,613 Solder-free PCB assembly
An electronic component assembly is disclosed. The electronic component assembly may comprise a printed circuit board, a frame secured to the printed circuit...
US-6,580,533 Two-way optical transmission and reception device
A transmission and reception device, in which the transmission device and the reception device and the input/output end of a glass fiber are disposed optically...
US-6,580,381 Analog-to-digital converter with complementary transistors
Located between the frustoconical needle tip and the cylindrical needle shank of a nozzle needle of a fuel injection valve is a frustoconical needle portion,...
US-6,580,334 Monolithically integrated transformer
A monolithic integrated transformer, especially for high frequency application in for example GSM-mobile components wherein a coupling factor is attained by...
US-6,580,326 High-bandwidth low-voltage gain cell and voltage follower having an enhanced transconductance
A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source...
US-6,580,311 Circuit configuration for supplying voltage to an integrated circuit via a pad
A circuit configuration for supplying voltage to an integrated circuit via a pad that is connected to the input of a Schmitt trigger on the integrated circuit....
US-6,580,118 Non-volatile semiconductor memory cell having a metal oxide dielectric, and method for fabricating the memory cell
A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer (10) is replaced by a very thin...
US-6,580,110 Trench capacitor and method for fabricating a trench capacitor
A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper...
US-6,579,786 Method for depositing a two-layer diffusion barrier
A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper...
US-6,579,768 Field effect transistor and method of fabrication
An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a...
US-6,579,766 Dual gate oxide process without critical resist and without N2 implant
A process as shown in FIGS. 1A through 1I, or FIGS. 2A through 2I for providing first areas of gate oxide (30, 30A, 30B) on a substrate (10) having a first...
US-6,579,759 Formation of self-aligned buried strap connector
In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode...
US-6,579,758 Method and installation for fabricating one-sided buried straps
Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a...
US-6,579,729 Memory cell configuration and method for fabricating it
Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element...
US-6,579,650 Method and apparatus for determining photoresist pattern linearity
Method and apparatus for determining photoresist pattern linearity. The method and apparatus comprises a substrate and a measuring pattern (26) printed on the...
US-6,577,528 Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration
A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections...
US-6,577,527 Method for preventing unwanted programming in an MRAM configuration
Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are...
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