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An analogue frontend, such as is used, for example, in receivers for communications equipment, comprises a plurality of analogue components (1-3) which are...
Differential line driver circuit
A differential line driver circuit having an output impedance matched to the line impedance includes first and second input terminals for the application of an...
Device for packaging electronic components
The invention relates to a device and a method for packaging electronic components (11) having semiconductor chips (5) by means of a mounting frame (1), which is...
Shielding device and electrical structural part having a shielding device
The shielding device described is distinguished by the fact that it has a coating that at least partially surrounds the element that is to be electromagnetically...
Mos transistor and dram cell configuration
A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form...
Method for forming dual damascene structure
A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an...
Method for fabricating a thin, free-standing semiconductor device layer and
for making a three-dimensionally...
In a method for fabricating a silicon-on-insulation wafer having fully processed devices in its upper-most silicon layer, the wafer is reduced in thickness from...
Semiconductor device with STI sidewall implant
A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably...
A coupling element for optical coupling of at least one optoelectronic transducer to at least one optical wave guide, with a coupling element having an image...
View DAC feedback inside analog front circuit
A view DAC feedback inside an analog front circuit for a partial response, maximum likelihood based read/write channel is disclosed. The view DAC feedback...
Integrated circuit for mobile radio and mobile telephone installations
Microwave circuit arrangement containing one or more semiconductor switching elements, which are characterized in that at least one semiconductor switching...
Push-pull output stage for digital signals with regulated output levels
The circuit has a push-pull end stage which acts as an amplifier stage for digital signals. The push-pull end stage has two n-channel MOS transistors which...
Circuit configuration for converting logic levels
The circuit configuration for converting logic levels has a bipolar input stage and a CMOS output stage. The bipolar input stage is equipped to process ECL and...
Vertical gate top engineering for improved GC and CB process windows
A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the...
Memory cell configuration with capacitor on opposite surface of substrate
and method for fabricating the same
A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on...
Dual layer hard mask for eDRAM gate etch process
A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes...
Apparatus and process for collecting trace metals from wafers
An improved process for cleaning a semiconductor wafer surface during manufacture to remove metallic contaminants without the use of robotics and without risk of...
On-chip debug system
An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an...
Random access memory with hidden bits
A random access memory having a multiplicity of memory cells having logic states that can be changed by a control voltage. At least some of the memory cells...
Integrated semiconductor memory having memory cells with a ferroelectric
An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a...
Clocked power supply
The integrable control circuit drives a semiconductor switch in a switched-mode power supply. The control circuit has a control unit for producing control pulses...
Circuit configuration for controlling nonlinear paths
An electrical circuit is provided for controlling nonlinear paths. A first linearization block and a second linearization block are provided, which may each have...
A flip-flop circuit comprises a master latch circuit (2), which receives an input signal (D), and, connected in series therewith, a slave latch circuit (3), the...
Method and circuit configuration for controlling a data driver
A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times...
Test structure in an integrated semiconductor
With increasing integration density of integrated circuits, the packing density in test regions (kerf structures) located between the integrated circuits cannot...
Contact connection of metal interconnects of an integrated semiconductor
An integrated semiconductor chip has at least two metal interconnects of two different metallization planes, which are disposed parallel to one another. The...
Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys
In an integrated circuit structure, the improvement comprising a wire bonded Cu-pad with Cu-wire component, wherein the Cu-pad Cu-wire component is characterized...
Field-effect-controlled transistor and method for fabricating the
An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface...
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING A PARTICULAR
FUNCTIONALITY REQUIRED BY A USER OF THE...
An integrated circuit has first structures that are produced in a plurality of wiring planes using exposure masks and serve for producing a functionality...
A bottom resist for the two-layer technique includes a phenolic base polymer, a thermoactive compound which above a temperature of 100.degree. C. releases a...
Coupling sleeve having a shielding plate
A coupling sleeve is described which contains a sleeve body with a passage opening for accommodating a coupling partner on both ends respectively. An ...
Method and device for decoding convolutional codes
Convolutional codes are decoded by calculating, for uncoded and coded symbols, a first and/or second item of reliability information (.LAMBDA..sub.u and...
Memory device with support for unaligned access
An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single...
Electronics amplifier circuit having a switchable input transistor, matrix
array of memory cells and matrix...
An electronic amplifier circuit according to the principle of current detection is coupled to a memory cell field and has an input transistor for each respective...
Device for evaluating cell resistances in a magnetoresistive memory
A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node,...
Low voltage charge pump for use in a phase locked loop
A low voltage charge pump for a phase locked loop is disclosed. The low voltage charge pump provides linear control for a voltage at a loop filter. The charge...
Capacitor with high-.epsilon. dielectric or ferroelectric material based on
the fin stack principle
A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of...
Semiconductor switching element that blocks in both directions
The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and...
Method of structuring a metal-containing layer
The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas...
Multiple exposure process for formation of dense rectangular arrays
A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the...
Device for reliability creating electronic signatures
A device for reliably creating electronic signatures that includes a data carrier read/write device, a data generating device, and a display device. The data...
Methods and apparatus for re-reordering command and data packets in order
to restore an original order of...
According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests...
A MRAM configuration in which the word lines have a low-resistance connection to the programming lines and the sources of the select transistors can be connected...
Method and device for digitally coding binary data with a particular
transmit signal spectrum
A coding device for coding binary data with a particular transmit signal spectrum, the coding device having a data stream separating device for separating a data...
Circuit and method for attenuating or eliminating undesired properties of
an operational amplifier
A compensation circuit for attenuating or eliminating undesired properties of an operational amplifier and a corresponding compensation method determine...
Charge pump and PLL
A charge pump has a reference stage that simulates the output stage of the paths, at least in terms of the output-side transistors of the paths. An equivalent...
Semiconductor fuses and antifuses in vertical DRAMS
A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor...
Process for protecting array top oxide
Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET...
Method for forming structures on a wafer
A method for fabricating a structure on an integrated circuit wafer, includes applying an anti-sticking coating to a surface of a mold, depositing a first...
Liquid transfer molding system for encapsulating semiconductor integrated
An encapsulation system is used to encapsulate semiconductor products. A bottom mold unit includes a mold pot and a mold piston. A substrate loader loads a...