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Memory cell configuration with capacitor on opposite surface of substrate
and method for fabricating the same
A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on...
Dual layer hard mask for eDRAM gate etch process
A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes...
Apparatus and process for collecting trace metals from wafers
An improved process for cleaning a semiconductor wafer surface during manufacture to remove metallic contaminants without the use of robotics and without risk of...
On-chip debug system
An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an...
Random access memory with hidden bits
A random access memory having a multiplicity of memory cells having logic states that can be changed by a control voltage. At least some of the memory cells...
Integrated semiconductor memory having memory cells with a ferroelectric
An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a...
Clocked power supply
The integrable control circuit drives a semiconductor switch in a switched-mode power supply. The control circuit has a control unit for producing control pulses...
Circuit configuration for controlling nonlinear paths
An electrical circuit is provided for controlling nonlinear paths. A first linearization block and a second linearization block are provided, which may each have...
A flip-flop circuit comprises a master latch circuit (2), which receives an input signal (D), and, connected in series therewith, a slave latch circuit (3), the...
Method and circuit configuration for controlling a data driver
A data driver is activated in dependence of a provided bit sequence in order to produce, at the data output of the driver, a data signal which, in the times...
Test structure in an integrated semiconductor
With increasing integration density of integrated circuits, the packing density in test regions (kerf structures) located between the integrated circuits cannot...
Contact connection of metal interconnects of an integrated semiconductor
An integrated semiconductor chip has at least two metal interconnects of two different metallization planes, which are disposed parallel to one another. The...
Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys
In an integrated circuit structure, the improvement comprising a wire bonded Cu-pad with Cu-wire component, wherein the Cu-pad Cu-wire component is characterized...
Field-effect-controlled transistor and method for fabricating the
An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface...
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT HAVING A PARTICULAR
FUNCTIONALITY REQUIRED BY A USER OF THE...
An integrated circuit has first structures that are produced in a plurality of wiring planes using exposure masks and serve for producing a functionality...
A bottom resist for the two-layer technique includes a phenolic base polymer, a thermoactive compound which above a temperature of 100.degree. C. releases a...
Coupling sleeve having a shielding plate
A coupling sleeve is described which contains a sleeve body with a passage opening for accommodating a coupling partner on both ends respectively. An ...
Method and device for decoding convolutional codes
Convolutional codes are decoded by calculating, for uncoded and coded symbols, a first and/or second item of reliability information (.LAMBDA..sub.u and...
Memory device with support for unaligned access
An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single...
Electronics amplifier circuit having a switchable input transistor, matrix
array of memory cells and matrix...
An electronic amplifier circuit according to the principle of current detection is coupled to a memory cell field and has an input transistor for each respective...
Device for evaluating cell resistances in a magnetoresistive memory
A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node,...
Low voltage charge pump for use in a phase locked loop
A low voltage charge pump for a phase locked loop is disclosed. The low voltage charge pump provides linear control for a voltage at a loop filter. The charge...
Capacitor with high-.epsilon. dielectric or ferroelectric material based on
the fin stack principle
A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of...
Semiconductor switching element that blocks in both directions
The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and...
Method of structuring a metal-containing layer
The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas...
Multiple exposure process for formation of dense rectangular arrays
A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the...
Device for reliability creating electronic signatures
A device for reliably creating electronic signatures that includes a data carrier read/write device, a data generating device, and a display device. The data...
Methods and apparatus for re-reordering command and data packets in order
to restore an original order of...
According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests...
A MRAM configuration in which the word lines have a low-resistance connection to the programming lines and the sources of the select transistors can be connected...
Method and device for digitally coding binary data with a particular
transmit signal spectrum
A coding device for coding binary data with a particular transmit signal spectrum, the coding device having a data stream separating device for separating a data...
Circuit and method for attenuating or eliminating undesired properties of
an operational amplifier
A compensation circuit for attenuating or eliminating undesired properties of an operational amplifier and a corresponding compensation method determine...
Charge pump and PLL
A charge pump has a reference stage that simulates the output stage of the paths, at least in terms of the output-side transistors of the paths. An equivalent...
Semiconductor fuses and antifuses in vertical DRAMS
A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor...
Process for protecting array top oxide
Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET...
Method for forming structures on a wafer
A method for fabricating a structure on an integrated circuit wafer, includes applying an anti-sticking coating to a surface of a mold, depositing a first...
Liquid transfer molding system for encapsulating semiconductor integrated
An encapsulation system is used to encapsulate semiconductor products. A bottom mold unit includes a mold pot and a mold piston. A substrate loader loads a...
Interface for a memory unit
An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal...
Circuit configuration for generating sense amplifier control signals
A circuit configuration for generating sense amplifier control signals for a DRAM. The circuit configuration includes, in addition to thin oxide transistors that...
Circuit configuration and method for accelerating aging in an MRAM
A circuit configuration and a method for accelerating aging in an MRAM, in which additional circuit are provided in order to feed a higher current into a control...
Method for selecting, prioritizing, and A/D conversion of analog signals,
and A/D converter configuration that...
A method for A/D conversion of analog signals using an A/D converter, and to an appropriate A/D converter circuit. In order to process converter request signals...
Semiconductor module with a number of semiconductor chips and a conductive
connection between the semiconductor...
A semiconductor module of the type having a number of semiconductor chips disposed on a chip carrier has at least a second subset of the semiconductor chips...
Method for manufacturing integrated circuits and semiconductor wafer which
has integrated circuits
A method for manufacturing integrated circuits is described. A semiconductor wafer having an active side with circuit structures is provided. An electrically...
Method and an apparatus for treating wastewater from a chemical-mechanical
polishing process used in chip...
Wastewater from a chemical-mechanical polishing process (CMP) used in semiconductor chip fabrication has hitherto been, and is still being, discharged into the...
Method and apparatus for processing defect addresses
A method and apparatus for processing defect addresses includes a reduced number of defect addresses to the extent necessary for later evaluation of the defect...
Integrated memory having memory cells with a magnetoresistive storage
property and method of operating such a...
An integrated memory has memory cells with a magnetoresistive storage property. The memory cells are connected in each case between column lines and row lines....
Integrated memory with plate line segments
The integrated memory has driver units DRVi, via which the column select lines CSLi are connected to the plate line segments PLi and which, as a function of the...
Method for configuring low-noise integrated amplifier circuits
A method for configuring low-noise integrated amplifier circuits having an input stage with a transistor includes noise matching the circuit to the real part of...
Output controlled line driver with programmable common mode control
A differential line driver having integrated output termination resistors is disclosed. The termination resistors are a combination of a controlled transistor...
Configuration for trimming reference voltages in semiconductor chips, in
particular semiconductor memories
A circuit configuration for trimming reference voltages in semiconductor chips. The circuit configuration contains a test logic unit and a trimming circuit for...
Method and device for testing electronic components
A method for testing electronic components includes the step of outputting test output data for the tested electronic components on a test board without...