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A reference stage is provided in order to compensate for manufacturing tolerances, for example relating to the threshold voltage of a transistor. This reference...
Secure asynchronous clock multiplexer
A system and method for clock multiplexing. According to one implementation, a pair of two stage cross-coupled clock gating elements are controlled by a single...
Integrated semiconductor circuit with an increased operating voltage
An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity...
Clock signal generator
A clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output (41), the clock signal generator (1) having:...
Configuration for carrying out burn-in processing operations of
semiconductor devices at wafer level
A configuration for carrying out burn-in processing for semiconductor devices at the wafer level. To this end, BIST units are allocated to the individual...
Component holder for testing devices and component holder system
A component holder for testing electronic components having a carrier, at least one component socket arranged on the carrier and having a group of component...
A thin film piezoresonator, which can be tuned over a wide range of RF frequencies, includes a piezo layer between a first electrode layer and a second electrode...
Low impedance VDMOS semiconductor component
A low impedance VDMOS semiconductor component having a planar gate structure is described. The VDMOS semiconductor component contains a semiconductor body of a...
Integrated dynamic memory cell having a small area of extent, and a method
for its production
An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate...
Process flow for sacrificial collar scheme with vertical nitride mask
A process flow for forming a sacrificial collar (132) within a deep trench (113) of a semiconductor memory cell. A nitride liner layer (120) is deposited over a...
Field effect transistor and method of fabrication
An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a...
Method for fabricating a memory cell configuration
A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming...
Method for mounting a semiconductor chip on a carrier layer and device for
carrying out the method
In order to mount a semiconductor chip on a carrier layer, consolidated filler material is applied between the semiconductor chip and the carrier layer. The...
Single-piece cage for pluggable fiber optic transceiver
A cage for mounting a pluggable fiber optic transceiver onto a host circuit board. The cage is entirely formed from a single blank, which is folded along...
Device for contactless transmission of data
A device for a contactless transmission of data includes a data transceiver with an antenna. The impedance of the antenna of the data transceiver is purposely...
Universal resource access controller
A universal access controller is described. The universal resource access controller is coupled to a requesting system and a resource, such that when the...
Filter for time division multiplex filtering of a plurality of data trains,
and operating methods therefor
A filter for filtering n data trains by time division multiplexing includes data channels for receiving data train values, registers subdivided into n groups for...
Integrated circuit card for computer communication
An interface circuit for allowing a computer system to communicate over existing household wiring in multiple frequency bands. The interface circuit includes an...
Integrated memory having a row access controller for activating and
deactivating row lines
An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row...
CIRCUIT CONFIGURATIONS HAVING A DELAY DEVICE, A MULTIPLIER, FILTER AND/OR A
MASTER-SLAVE FLIP-FLOP FOR...
A circuit configuration for generating an output signal orthogonal to an input signal includes a delay device having an input to which an input signal is...
Device for reducing the electromagnetic emission in integrated circuits
with driver stages
A device for reducing the electromagnetic emission in integrated circuits having driver stages reduces the electromagnetic emission of an integrated circuit...
Semiconductor power component with a reduced parasitic bipolar transistor
A semiconductor power component has a MOS structure in which the source region is formed of a material whose band gap is smaller than the band gap of the...
Bis-o-aminophenols and o-aminophenolcarboxylic acids and process for
preparing the same
Bis-o-aminophenols and o-aminophenolcarboxylic acids have the following structures: ##STR1## A.sup.1 to A.sup.7 are, independently of each other, H, F,...
Method for low temperature chemical vapor deposition of low-k films using
selected cyclosiloxane and ozone...
A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling...
Method for processing wafer by applying layer to protect the backside
during a tempering step and removing...
A method for processing a monocrystalline Si-semiconductor wafer includes a tempering step at a temperature of over 550.degree. C. A protective layer for...
Method for high aspect ratio gap fill using sequential HDP-CVD
A method of providing isolation between element regions of a semiconductor memory device (200). Isolation trenches (211) are filled using several sequential...
Method for fabricating a memory cell array
A method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, includes burying insulation zones on a silicon substrate in...
Method and apparatus for an easy identification of a state of a DRAM
In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a...
Low-noise mixer and method
A mixer circuit for downconverting a radio frequency signal to a lower (intermediate) frequency signal or upconverting an intermediate frequency signal to a...
Optical fiber for optically coupling a light radiation source to a
multimode optical waveguide, and method for...
Optical fiber for optically coupling a light radiation source to a multimode optical waveguide, and method for manufacturing it. Optical fiber for optically...
Circuit configuration for controlling the operating point of a power
A circuit configuration for actuating a power amplifier transistor is described, which is intended to ensure that the power consumption is as low as possible...
Prefetch architectures for data and time signals in an integrated circuit
and methods therefor
A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to...
Area efficient clock inverting circuit for design for testability
A method for fabricating IC devices including both rising edge-triggered circuits (e.g., flip-flops or latches) and falling edge-triggered circuits in which a...
Integrated circuit configuration for testing transistors, and a
semiconductor wafer having such a circuit...
Circuit configurations for testing transistors are arranged in the scribe line between integrated circuits on a semiconductor wafer. In order to increase the...
Configuration for testing a plurality of memory chips on a wafer
A configuration for testing a plurality of memory chips on a wafer, in which needles are used to supply the memory chips with supply voltages, an initialization...
Semiconductor component having a chip carrier with openings for making
A semiconductor component includes a chip carrier having a first surface, a second surface, and openings therein. At least one semiconductor chip is mounted on...
MOSFET having a low aspect ratio between the gate and the source/drain
A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on...
Biometric sensor and method for its production
In a biometric sensor and a method for its production, a sensor chip is provided with connecting contacts in the form of electrically conductive bumps. The...
Method for monitoring nitrogen processes
The novel method allows monitoring of nitrogen processes by making use of the fact that the incorporation of nitrogen near the surface in silicon, or in a thin...
Dicing configuration for separating a semiconductor component from a
The dicing configuration for separating a semiconductor component from a semiconductor wafer is formed with a rupture joint which is created together with...
Method for manufacturing a trench capacitor
A method for manufacturing a trench capacitor uses a low-pressure gas phase doping for forming a buried plate as a capacitor plate. The use of the low-pressure...
Simultaneous formation of deep trench capacitor and resistor
A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular...
Method for fabricating a trench MOS power transistor
A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the...
Complex of an element of transition group IV or V for forming an improved
A new complex of an element of transition group IV or V is provided for forming an improved precursor combination for use in chemical vapor deposition (CVD)....
Methods and apparatus for reordering of the memory requests to achieve
higher average utilization of the...
According to the present invention, a scheduler suitable for reordering of memory requests to achieve higher average utilization of the command and data bus is...
Method and apparatus for determining interpolated intermediate values of a
A method and apparatus determines interpolated intermediated values of a sampled signal. In order to determine interpolated intermediate values of a sampled...
Circuit configuration for evaluating the information content of a memory
A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a...
A circuit configuration prevents a transfer of interference signals present on an input line to a processing section. Electrical input signals are evaluated in...
Integrated memory with redundancy
An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two...
Programmable read-only memory and method for operating the read-only memory
A programmable read-only memory and a method for operating the read-only memory are described. The memory contains at least one memory cell field with a...