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Patent # Description
US-6,551,874 Self-aligned STI process using nitride hard mask
A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep...
US-6,550,982 Optoelectronic surface-mountable module and optoelectronic coupling unit
An optoelectronic module is disclosed, which can be connected optically and electrically in a simply way. The optoeletronic module consists of a SMD-housing (1)...
US-6,550,127 Device for holding a part and application of the device
A device for holding a part comprises a retainer member provided for applying and holding the part and having a convexly spherical surface section which is...
US-6,549,961 Semaphore access in a multiprocessor system
Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each...
US-6,549,588 Communications system and corresponding receiver unit
Angle-modulated signals are transmitted in a communications system, in which coding information has been inserted into the transmitted data at regular intervals....
US-6,549,354 Acquisition signal error estimator
A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample...
US-6,549,080 Electronic circuit, particularly for a mobile transceiver
A phase-locked loop circuit is described and has a digital circuit section and an analog circuit section that are fed with different supply voltages. Control...
US-6,549,063 Evaluation circuit for an anti-fuse
The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged...
US-6,549,028 Configuration and process for testing a multiplicity of semiconductor chips on a wafer plane
Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a...
US-6,548,882 Power transistor cell
A power transistor cell includes an air bridge and a plurality of individual transistors. Each of the plurality of individual transistors has at least one...
US-6,548,861 Memory cell, memory cell arrangement and fabrication method
An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the...
US-6,548,850 Trench capacitor configuration and method of producing it
A trench capacitor is formed in a substrate and includes a trench having an upper region and a lower region. An insulating collar is formed in the upper region...
US-6,548,846 Storage capacitor for a DRAM
A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric....
US-6,548,414 Method of plasma etching thin films of difficult to dry etch materials
A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at...
US-6,548,357 Modified gate processing for optimized definition of array and logic devices on same chip
Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region,...
US-6,548,350 Method of fabricating an integrated circuit configuration with at least one capacitor
The capacitor is arranged on the surface of a substrate. A first capacitor electrode has a middle part and a side part, which point vertically upwards, are...
US-6,548,344 Spacer formation process using oxide shield
In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation...
US-6,548,341 Process for producing a first electrode and a second electrode, electronic component and electronic memory element
In a process for producing a first electrode and a second electrode, the first electrode and the second electrode are provided on an electrode material. A...
US-6,548,314 Method for enabling access to micro-sections of integrated circuits on a wafer
The present invention provides a method of enabling measurement access to small integrated circuit features that comprises selecting a feature of an integrated...
US-6,545,930 Integrated memory having a voltage regulating circuit
An integrated memory has a memory cell array with row lines and column lines. A row decoder for activating row lines is connected to address lines for...
US-6,545,927 Integrated semiconductor circuit, in particular a semiconductor memory configuration, and method for its operation
An integrated semiconductor circuit, in particular a semiconductor memory configuration, which can be operated in various operating modes and which has an...
US-6,545,905 Multi-port memory cell with refresh port
A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to...
US-6,545,900 MRAM module configuration
An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in...
US-6,545,881 Method for regulating a switched-mode power supply and switched-mode power supply
A method for regulating a switched-mode power supply includes steps of: providing a switched-mode power supply having at least one electronic switch and a drive...
US-6,545,625 Method and device for data exchange between memory and logic modules
The method and the device are particularly suitable for data exchange between memory modules and logic modules. A multidigit digital signal at the transmitter...
US-6,545,526 Fuse circuit configuration
A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection...
US-6,545,517 Frequency splitter circuit
A frequency splitter circuit includes only two differential amplifiers. A clock input signal is supplied to clock signal inputs for activating the amplifiers. A...
US-6,544,856 Method for increasing the trench capacitance
A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a...
US-6,544,855 Process flow for sacrificial collar with polysilicon void
A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within...
US-6,544,853 Reduction of negative bias temperature instability using fluorine implantation
A process of fabricating a p-type metal oxide semiconductor to affect reduction of negative bias temperature instability (NBTI) in the formed p-type metal oxide...
US-6,544,850 Dynamic random access memory
A dynamic random access memory (DRAM) formed in a silicon chip that includes a support area in which support circuitry of the memory includes a single electrical...
US-6,544,838 Method of deep trench formation with improved profile control and surface area
A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench...
US-6,543,045 Method for detecting and automatically eliminating phase conflicts on alternating phase masks
A method for eliminating phase conflicts that occur in the layout of a phase mask in a localized and automated manner. The method includes a first step in which...
US-6,542,837 Wafer processing system
A wafer processing system is described located in at least one clean room and having an arrangement of manufacturing units for performing individual ...
US-6,542,604 Scaled impedance replica for echo attenuation in digital transmission systems
A device for echo attenuation in a digital transmission system comprises an impedance replica of the transmission path. The impedance replica consists of a...
US-6,542,430 Integrated memory and memory configuration with a plurality of memories and method of operating such a memory...
A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the...
US-6,542,395 Integrated DRAM memory module
The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are...
US-6,542,389 Voltage pump with switch-on control
The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a...
US-6,542,100 Apparatus and method for filtering a signal which represents a digital data stream
A signal to be produced, which represents a digital data stream, is generated using the currents or voltages from current or voltage sources selected from...
US-6,542,054 Acoustic mirror and method for producing the acoustic mirror
An acoustic mirror is described which is formed of at least one first insulating layer, a first metal layer disposed thereon, a second insulating layer disposed...
US-6,541,999 Circuit configuration with temperature protection and method for implementing the temperature protection
A configuration for protecting an integrated circuit against over-temperature conditions is described. The configuration has at least one detector device, which...
US-6,541,833 Micromechanical component with sealed membrane openings and method of fabricating a micromechanical component
The method for producing a micromechanical component includes the following steps: producing a semi-finished micromechanical component; producing openings and...
US-6,541,818 Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer...
A field effect transistor configuration with a trench gate electrode and a method for producing the same. An additional highly doped layer is provided in the...
US-6,541,804 Junction-isolated lateral MOSFET for high-/low-side switches
The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain...
US-6,541,387 Process for implementation of a hardmask
A resist layer is deposited atop a substrate and is patterned to expose portions of a substrate. A hardmask layer is deposited atop the patterned resist layer...
US-6,541,372 Method for manufacturing a conductor structure for an integrated circuit
A simple to manufacture conductor structure is described which requires only a small number of process steps. The conductor structure contains a structured,...
US-6,541,334 Integrated circuit configuration having at least one buried circuit element and an insulating layer, and a...
The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with...
US-6,541,311 Method of positioning a component mounted on a lead frame in a test socket
A lead frame is configured with conductor leads, a dam bar and an extension between the conductor leads. The extension projects from the dam bar toward a central...
US-6,540,555 Shielding plate, in particular for optoelectronic transceivers
The shielding plate is particularly suited for optoelectronic transceivers. The shielding plate is a hollow body in the form of a casing and has contact springs...
US-6,540,413 Fiber-optic transmitting component with precisely settable input coupling
In a fiber-optic transmitting component, either an adjusting sleeve (3) or a fiber flange is provided with a polarization filter (5) and an adjustment step is...
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