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Patent # Description
US-6,560,134 Memory configuration with a central connection area
A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory...
US-6,559,897 Method for random access to picture blocks in video pictures
During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient...
US-6,559,786 Circuit arrangement for conversion of an input current signal to a corresponding digital output signal
The invention provides a circuit arrangement for conversion of an input current signal (11) to a digital output signal (43). In particular, the invention relates...
US-6,559,785 Digital/analog converter
Digital/analog converter for converting a binary coded data word into an analog output signal, having a capacitor cell Matrix (9) comprising capacitor cells...
US-6,559,721 Circuit configuration with an integrated amplifier
A circuit configuration with an integrated amplifier is described. The amplifier has an output stage that is connected to a supply potential terminal and a...
US-6,559,716 Switchable operational amplifier for switched op-amp applications
A switchable operational amplifier is presented for switched op amp technology, in which the current through the pre-stage is reduced during the off phase of the...
US-6,559,547 Patterning of content areas in multilayer metalization configurations of semiconductor components
The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact...
US-6,559,503 Transistor with ESD protection
The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or...
US-6,559,069 Process for the electrochemical oxidation of a semiconductor substrate
In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a...
US-6,559,067 Method for patterning an organic antireflection layer
An antireflection coating (ARC) polymer layer is patterned by DUV (deep ultraviolet) lithography followed by an ARC open etching step and subsequent etching of...
US-6,559,005 Method for fabricating capacitor electrodes
The method according to the invention enables the roughness of an HSG surface to be substantially transferred to the surface of an electrode. The electrode...
US-6,559,003 Method of producing a ferroelectric semiconductor memory
A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to...
US-6,559,002 Rough oxide hard mask for DT surface area enhancement for DT DRAM
In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not...
US-6,558,883 Apparatus and method for patterning a semiconductor wafer
A method and apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the...
US-6,558,770 Perforated work piece, and method for producing it
A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are...
US-6,558,196 Shielding plate for pluggable electrical components
The shielding plate receives pluggable electrical components, in particular optoelectronic transceivers. The shielding plate has an at least partially ...
US-6,557,769 Smart card module, smart card with the smart card module, and method for producing the smart card module
Flip-chip bumps (solder bumps) are applied on the contact-connection points of a semiconductor chip. These bumps extend from there through a covering compound...
US-6,557,085 Circuit configuration for handling access contentions
The circuit handles access contentions in memories with a plurality of mutually independent, addressable I/O ports. There are provided two subcircuits, namely...
US-6,556,496 Semiconductor configuration with optimized refresh cycle
A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is...
US-6,556,492 System for testing fast synchronous semiconductor circuits
The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe...
US-6,556,486 Circuit configuration and method for synchronization
A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the...
US-6,556,418 Micromechanical component and process for its fabrication
A micromechanical component placed on a substrate face includes at least one cell. A counter-electrode of a cell capacitor is placed under a cavity. The...
US-6,556,164 Analog/digital converter and method for converting an analog input signal into a digital output signal
An analog-to-digital converter for successively and approximately converting an analog input signal into a digital output signal includes at least one comparator...
US-6,556,070 Current source that has a high output impedance and that can be used with low operating voltages
An electrical current source with a high output resistance has a current determining transistor and a regulating switch. The regulating switch has an amplifier...
US-6,555,862 Self-aligned buried strap for vertical transistors
A semiconductor device formed by a method for aligning a strap diffusion, in accordance with the invention, includes the steps of providing a trench in a...
US-6,555,849 Deactivatable thyristor
A thyristor includes a semiconductor body having a first emitter layer and a first base layer on an anode side, a second base layer and a second emitter layer on...
US-6,555,415 Electronic configuration with flexible bonding pads
An electronic configuration has a first surface with electrical contacts for electrical bonding. The configuration includes at least one flexible elevation made...
US-6,554,493 Configuration for coupling optoelectronic elements and fiber arrays
A coupling configuration is described which contains optoelectronic elements having optically active zones, a coupling element, and optical waveguide sections...
US-6,553,521 Method for efficient analysis semiconductor failures
The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a...
US-6,553,424 Circular buffer for a TDMA data transmission station and corresponding data transmission station
A circular buffer for a TDMA data transmission station temporarily stores digital transmit data occurring over a number of time slots in the transmission station...
US-6,553,157 Optoelectronic microelectronic system
In an integrated optoelectronic microelectronic system, an optoelectronically active diode part is formed in a semiconductor substrate by zones forming depletion...
US-6,552,951 Dual-port memory location
The invention relates to a dual-port DRAM memory location having a capacitor and two transfer gates whose load paths are connected in series. The series...
US-6,552,865 Diagnostic system for a read/write channel in a disk drive
The invention provides a read/write channel with a diagnostic system for a disk drive. The diagnostic system may process internal and external signals. The...
US-6,552,599 Diode circuit with ideal diode characteristic
A circuit configuration produces an at least approximately ideal diode characteristic on the basis of a diode. A power MOSFET has a control path connected in...
US-6,552,593 Active auto zero circuit for programmable time continuous open loop amplifiers
An active offset cancellation circuit for an open loop differential amplifier having programmable gain is disclosed. The amplifier is operated on a two-phase...
US-6,552,549 Method of reading electrical fuses/antifuses
Electrical fuses/antifuses in a semiconductor memory configuration, such as in particular a DRAM, are read, instead of with the previously conventional internal...
US-6,552,385 DRAM memory capacitor having three-layer dielectric, and method for its production
A DRAM capacitor is described that contains a BaSrTiO.sub.3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential...
US-6,552,378 Ultra compact DRAM cell and method of making
A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic...
US-6,552,331 Device and method for combining scanning and imaging methods in checking photomasks
An apparatus and method for imaging and scanning masks for semiconductor production includes placing a scanning instrument having a probe at a position to scan a...
US-6,551,911 Method for producing Schottky diodes and Schottky diodes
A method for producing Schottky diodes having a protective ring in an edge region of a Schottky contact. The protective ring is produced by a protective ring...
US-6,551,902 Process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate
A laterally insulated buried zone of increased conductivity is fabricated in a semiconductor substrate. First, a reference layer is formed on a substrate with a...
US-6,551,874 Self-aligned STI process using nitride hard mask
A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep...
US-6,550,982 Optoelectronic surface-mountable module and optoelectronic coupling unit
An optoelectronic module is disclosed, which can be connected optically and electrically in a simply way. The optoeletronic module consists of a SMD-housing (1)...
US-6,550,127 Device for holding a part and application of the device
A device for holding a part comprises a retainer member provided for applying and holding the part and having a convexly spherical surface section which is...
US-6,549,961 Semaphore access in a multiprocessor system
Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each...
US-6,549,588 Communications system and corresponding receiver unit
Angle-modulated signals are transmitted in a communications system, in which coding information has been inserted into the transmitted data at regular intervals....
US-6,549,354 Acquisition signal error estimator
A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample...
US-6,549,080 Electronic circuit, particularly for a mobile transceiver
A phase-locked loop circuit is described and has a digital circuit section and an analog circuit section that are fed with different supply voltages. Control...
US-6,549,063 Evaluation circuit for an anti-fuse
The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged...
US-6,549,028 Configuration and process for testing a multiplicity of semiconductor chips on a wafer plane
Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a...
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