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Multi-port memory cell with refresh port
A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to...
MRAM module configuration
An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in...
Method for regulating a switched-mode power supply and switched-mode power
A method for regulating a switched-mode power supply includes steps of: providing a switched-mode power supply having at least one electronic switch and a drive...
Method and device for data exchange between memory and logic modules
The method and the device are particularly suitable for data exchange between memory modules and logic modules. A multidigit digital signal at the transmitter...
Fuse circuit configuration
A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection...
Frequency splitter circuit
A frequency splitter circuit includes only two differential amplifiers. A clock input signal is supplied to clock signal inputs for activating the amplifiers. A...
Method for increasing the trench capacitance
A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a...
Process flow for sacrificial collar with polysilicon void
A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within...
Reduction of negative bias temperature instability using fluorine
A process of fabricating a p-type metal oxide semiconductor to affect reduction of negative bias temperature instability (NBTI) in the formed p-type metal oxide...
Dynamic random access memory
A dynamic random access memory (DRAM) formed in a silicon chip that includes a support area in which support circuitry of the memory includes a single electrical...
Method of deep trench formation with improved profile control and surface
A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench...
Method for detecting and automatically eliminating phase conflicts on
alternating phase masks
A method for eliminating phase conflicts that occur in the layout of a phase mask in a localized and automated manner. The method includes a first step in which...
Wafer processing system
A wafer processing system is described located in at least one clean room and having an arrangement of manufacturing units for performing individual ...
Scaled impedance replica for echo attenuation in digital transmission
A device for echo attenuation in a digital transmission system comprises an impedance replica of the transmission path. The impedance replica consists of a...
Integrated memory and memory configuration with a plurality of memories and
method of operating such a memory...
A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the...
Integrated DRAM memory module
The integrated DRAM memory module has sense amplifiers which are each formed, in the integrated module, from a multiplicity of transistor structures that are...
Voltage pump with switch-on control
The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a...
Apparatus and method for filtering a signal which represents a digital data
A signal to be produced, which represents a digital data stream, is generated using the currents or voltages from current or voltage sources selected from...
Acoustic mirror and method for producing the acoustic mirror
An acoustic mirror is described which is formed of at least one first insulating layer, a first metal layer disposed thereon, a second insulating layer disposed...
Circuit configuration with temperature protection and method for
implementing the temperature protection
A configuration for protecting an integrated circuit against over-temperature conditions is described. The configuration has at least one detector device, which...
Micromechanical component with sealed membrane openings and method of
fabricating a micromechanical component
The method for producing a micromechanical component includes the following steps: producing a semi-finished micromechanical component; producing openings and...
Field-effect transistor configuration with a trench-shaped gate electrode
and an additional highly doped layer...
A field effect transistor configuration with a trench gate electrode and a method for producing the same. An additional highly doped layer is provided in the...
Junction-isolated lateral MOSFET for high-/low-side switches
The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain...
Process for implementation of a hardmask
A resist layer is deposited atop a substrate and is patterned to expose portions of a substrate. A hardmask layer is deposited atop the patterned resist layer...
Method for manufacturing a conductor structure for an integrated circuit
A simple to manufacture conductor structure is described which requires only a small number of process steps. The conductor structure contains a structured,...
Integrated circuit configuration having at least one buried circuit element
and an insulating layer, and a...
The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with...
Method of positioning a component mounted on a lead frame in a test socket
A lead frame is configured with conductor leads, a dam bar and an extension between the conductor leads. The extension projects from the dam bar toward a central...
Shielding plate, in particular for optoelectronic transceivers
The shielding plate is particularly suited for optoelectronic transceivers. The shielding plate is a hollow body in the form of a casing and has contact springs...
Fiber-optic transmitting component with precisely settable input coupling
In a fiber-optic transmitting component, either an adjusting sleeve (3) or a fiber flange is provided with a polarization filter (5) and an adjustment step is...
Chromium adhesion layer for copper vias in low-k technology
In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by...
Method of testing a semiconductor memory, and semiconductor memory with a
In order to test a semiconductor memory, a bit fail map is generated in that a predetermined data value is written to memory cells and subsequently read out and...
Methods and apparatus for prediction of the time between two consecutive
According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is...
Module for multiplexing and/or demultiplexing optical signals
The invention relates to a module for multiplexing and/or demultiplexing optical signals, having at least one wavelength-selective filter for multiplexing or...
Apparatus for sidetone damping
An apparatus for sidetone damping can be used in telephones configured for hands-free operation. The apparatus has a reception branch with a speaker and a...
Integrable radio receiver circuit for frequency-modulated digital signals
An FM receiver, which contains quadrature downward mixing to a low IF, analog IF polyphase filters in quadrature signal paths and an analog quadrature signal...
Integrated memory and corresponding operating method
An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit...
Memory employing multiple enable/disable modes for redundant elements and
testing method using same
A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each...
Method for operating a ferroelectric memory configuration and a
ferroelectric memory configuration
The invention relates to a method for operating a ferroelectric memory configuration in the V.sub.DD /2 mode. The memory configuration has a large number of...
TSOP memory chip housing configuration
A configuration of at least two TSOP memory chip housings stacked one on another, is described. Each of the TSOP memory chip housings has at least one memory...
Ferroelectric transistor and method for fabricating it
A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic...
Method for the positionally accurate adjustment and fixing of a
The inventor relates to method for the posibility accurate adjustment and fixing of a microoptical element on a carrier. In this case, an optical position...
Process for improving the thickness uniformity of a thin oxide layer in
semiconductor wafer fabrication
A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A...
Method for patterning a metal or metal silicide layer and a capacitor
structure fabricated by the method
In a method for fabricating a high-epsilon dielectric/ferroelectric capacitor, a patterning layer with a central base layer zone and a Si-filled trench laterally...
Transistor and method of manufacturing a transistor having a shallow
junction formation using a two step EPI layer
A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is...
Method of forming an integrated circuit comprising a self aligned trench
An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., 128,...
Semiconductor structures and manufacturing methods
A semiconductor body having an alignment mark comprising a pair of sets of parallel lines disposed on the semiconductor body, the parallel lines in one of the...
Coupling configuration for connecting an optical fiber to an optoelectronic
A coupling configuration for connecting an optical fiber provided with a coupling end face at one end to an optoelectronic element is described. A coupling...
Testable read-only memory for data memory redundant logic
The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units....
Circuit configuration for an integrated semiconductor memory with column
A circuit configuration for an integrated semiconductor memory has memory cells which are configured in a matrix-type memory cell array and which are combined to...
Display unit for chip cards with folded sheet a method for manufacturing
such a display unit
A display unit includes activation or driver electronics disposed on the rear side of a display element. A display unit has a front region with a display...