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Patent # Description
US-6,580,903 Circuit and method for recording and playing back voice and other sounds in digital mobile radio devices
A circuit for recording and playing back voice in digital mobile radio devices and a method for appropriately recording and playing back the voice. The circuit...
US-6,580,865 Optical fiber systems
An optical fiber system that enables direct board-to-board optical communication is described. The optical fiber system does not require data transmission...
US-6,580,831 Compression of optical readout biomolecular sensory data
The present invention provides a system and method for compression of image data while preserving the usable information and eliminating or reducing associated...
US-6,580,655 Pre-charge circuit and method for memory devices with shared sense amplifiers
A pre-charge circuit for a memory device having a sense amplifier shared between right and left banks of memory cells and a method of pre-charging the shared...
US-6,580,636 Magnetoresistive memory with a low current density
The magnetoresistive memory has a reduced current density in the bit lines and/or word lines. This avoids electromigration problems. The current density is...
US-6,580,613 Solder-free PCB assembly
An electronic component assembly is disclosed. The electronic component assembly may comprise a printed circuit board, a frame secured to the printed circuit...
US-6,580,533 Two-way optical transmission and reception device
A transmission and reception device, in which the transmission device and the reception device and the input/output end of a glass fiber are disposed optically...
US-6,580,381 Analog-to-digital converter with complementary transistors
Located between the frustoconical needle tip and the cylindrical needle shank of a nozzle needle of a fuel injection valve is a frustoconical needle portion,...
US-6,580,334 Monolithically integrated transformer
A monolithic integrated transformer, especially for high frequency application in for example GSM-mobile components wherein a coupling factor is attained by...
US-6,580,326 High-bandwidth low-voltage gain cell and voltage follower having an enhanced transconductance
A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source...
US-6,580,311 Circuit configuration for supplying voltage to an integrated circuit via a pad
A circuit configuration for supplying voltage to an integrated circuit via a pad that is connected to the input of a Schmitt trigger on the integrated circuit....
US-6,580,118 Non-volatile semiconductor memory cell having a metal oxide dielectric, and method for fabricating the memory cell
A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer (10) is replaced by a very thin...
US-6,580,110 Trench capacitor and method for fabricating a trench capacitor
A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper...
US-6,579,786 Method for depositing a two-layer diffusion barrier
A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper...
US-6,579,768 Field effect transistor and method of fabrication
An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a...
US-6,579,766 Dual gate oxide process without critical resist and without N2 implant
A process as shown in FIGS. 1A through 1I, or FIGS. 2A through 2I for providing first areas of gate oxide (30, 30A, 30B) on a substrate (10) having a first...
US-6,579,759 Formation of self-aligned buried strap connector
In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode...
US-6,579,758 Method and installation for fabricating one-sided buried straps
Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a...
US-6,579,729 Memory cell configuration and method for fabricating it
Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element...
US-6,579,650 Method and apparatus for determining photoresist pattern linearity
Method and apparatus for determining photoresist pattern linearity. The method and apparatus comprises a substrate and a measuring pattern (26) printed on the...
US-6,577,528 Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration
A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections...
US-6,577,527 Method for preventing unwanted programming in an MRAM configuration
Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are...
US-6,577,526 Magnetoresistive element and the use thereof as storage element in a storage cell array
The magnetoresistive element has a first ferromagnetic element, a nonmagnetic layer element, and a second ferromagnetic layer element arranged in such a way that...
US-6,577,509 Semiconductor circuit and switch-mode power supply
The invention relates to a semiconductor circuit having a drive circuit, a load that is disposed between a supply voltage, and a controllable, clocked...
US-6,577,196 Method and circuit for automatic gain control of a signal amplifier
Automatic gain control circuit for setting the gain of a signal amplifier having a peak value detector for measuring signal amplitudes of the analogue signal...
US-6,576,995 Housing for semiconductor chips
A housing for semiconductor chips includes a plastic base substrate having a region for accommodating a chip and substrate sides having a patterned metallization...
US-6,576,953 Vertical semiconductor component with source-down design and corresponding fabrication method
The present invention provides a semiconductor component having a substrate (10) of a first conduction type (n.sup.+); provided on the substrate (10), an...
US-6,576,948 Integrated circuit configuration and method for manufacturing it
An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a...
US-6,576,944 Self-aligned nitride pattern for improved process window
A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first...
US-6,576,565 RTCVD process and reactor for improved conformality and step-coverage
An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber...
US-6,576,550 `Via first` dual damascene process for copper metallization
An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The...
US-6,576,150 Process for the production of a glass article having at least one recess
An etching mask with at least one etching window is applied on a glass object consisting substantially of boron silicate glass. Subsequently, the glass object is...
US-6,575,790 Detachable connecting system
A detachable connecting system includes a component and a mount having cooperating guides which effect a defined movement of the component in a mounting...
US-6,574,413 Arrangement and method for the channel-dependent attenuation of the levels of a plurality of optical data channels
The invention relates to an arrangement and a method for the channel-dependent attenuation of the levels of a plurality of optical data channels which each...
US-6,574,390 Configuration to multiplex and/or demultiplex the signals of a plurality of optical data channels and method...
The invention relates to an arrangement for multiplexing and/or demultiplexing the signals of a plurality of optical data channels of different wavelength, in...
US-6,574,291 Turbo-code decoder and turbo-code decoding method with iterative channel parameter estimation
A turbo-code decoder with iterative channel parameter estimation for decoding turbo-coded received data that includes systematic information data and redundant...
US-6,574,155 Redundant multiplexer for a semiconductor memory configuration
A redundant multiplexer, in which the addresses of two series-connected switches are compared, and the switches are possibly interchanged, to ensure that no...
US-6,574,138 Memory cell configuration and method for operating the configuration
A memory cell configuration has memory cells that each contain two magnetoresistive elements. If the two magnetoresistive elements of each memory cell are...
US-6,574,132 Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits
The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the...
US-6,573,796 Automatic LDMOS biasing with long term hot carrier compensation
Disclosed are systems and methods for automatic biasing of LDMOS devices at turn-on. The invention provides bias point setting with compensation for hot carrier...
US-6,573,754 Circuit configuration for enabling a clock signal in a manner dependent on an enable signal
A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The...
US-6,573,593 Integrated circuit with a housing accommodating the integrated circuit
An integrated circuit having a housing accommodating the integrated circuit. It being possible for the integrated circuit to be put optionally into one of a...
US-6,573,561 Vertical MOSFET with asymmetrically graded channel doping
Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are...
US-6,573,542 Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer
The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an...
US-6,573,192 Dual thickness gate oxide fabrication method using plasma surface treatment
A method of forming on a common semiconductor body (substrate) silicon oxide layers of different thicknesses uses plasma treatment on selected portions of an...
US-6,573,145 Process for producing an MOS field effect transistor with a recombination zone
A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination...
US-6,573,136 Isolating a vertical gate contact structure
The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust...
US-6,572,280 Optical transmitting/receiving module including an internal optical waveguide
A module essentially includes a module housing, into which is introduced a lead frame. An electro-optical transducer is mounted on the lead frame. The interior...
US-6,571,383 Semiconductor device fabrication using a photomask designed using modeling and empirical testing
A method of fabricating a semiconductor device is outlined in FIG. 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A...
US-6,571,320 Cache memory for two-dimensional data fields
The cache memory is particularly suitable for processing images. The special configuration of a memory field, an allocation unit, a write queue, and a data...
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