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Patent # Description
US-6,567,300 Narrow contact design for magnetic random access memory (MRAM) arrays
An MRAM device (200) and method of manufacturing thereof having second conductive lines (228) with a narrow width. The second conductive lines (228) partially...
US-6,566,273 Etch selectivity inversion for etching along crystallographic directions in silicon
Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One...
US-6,566,271 Method of producing a semiconductor surface covered with fluorine
Fluorine is deposited on a semiconductor substrate surface according to a novel process. A semiconductor substrate is placed in a reaction chamber and the...
US-6,566,238 Metal wire fuse structure with cavity
An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes...
US-6,566,228 Trench isolation processes using polysilicon-assisted fill
Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the...
US-6,566,227 Strap resistance using selective oxidation to cap DT poly before STI etch
A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a...
US-6,566,220 Method for fabricating a semiconductor memory component
The invention relates to a method for fabricating a semiconductor memory component, in particular a DRAM or FeRAM having a silicon substrate. The lower electrode...
US-6,566,219 Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the...
A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g.,...
US-6,566,193 Method for producing a cell of a semiconductor memory
The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the...
US-6,566,187 DRAM cell system and method for producing same
DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a...
US-6,566,182 DRAM memory cell for DRAM memory device and method for manufacturing it
A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which...
US-6,565,263 Optical plug-in connector
The plug connector extends along a main axis and at least one optical waveguide end terminates in a connector housing. Locking parts, which are preferably...
US-6,564,469 Device for performing surface treatment on semiconductor wafers
A device for performing surface treatment on semiconductor wafers has a cassette (1) for accommodating a plurality of wafers (5) in its interior (3); the wafers...
US-6,564,346 Advanced bit fail map compression with fail signature analysis
A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed...
US-6,563,870 Nonlinear echo compensator
A nonlinear echo compensator for an L-level message signal includes a plurality of groups of coefficient memories, wherein each group is assigned to at least one...
US-6,563,867 Arrangement for analyzing the nonlinear properties of a communication channel
An arrangement to analyze the nonlinear properties of a communication channel that uses a test signal having a number of tones. The test signal is transmitted...
US-6,563,729 Configuration for evaluating a signal which is read from a ferroelectric storage capacitor
A configuration is described for evaluating a signal that is read from a ferroelectric storage capacitor, in which, in addition to positive and negative...
US-6,563,368 Integrable current supply circuit with parasitic compensation
Integrable current supply circuit An integrable current supply circuit for feeding a supply current to a signal line (12) having a current source (14) for...
US-6,563,201 System carrier for a semiconductor chip having a lead frame
A system substrate for a semiconductor chip has a conductor frame (1); many small-area signal flat conductors (4) extend from webs (2, 3) of the conductor frame...
US-6,563,179 MOS transistor and method for producing the transistor
Terminal regions of source/drain zones of an MOS transistor are configured over the substrate in the form of conductive structures, are separated from the...
US-6,561,854 Connection system
A connecting system for detachably mechanically connecting an electronic component to a support is described. The connecting system has fixed rails that are...
US-D474,473 Multimedia chip card
US-6,560,732 Operating method for an integrated memory having writeable memory cells and corresponding integrated memory
Before a write and/or read access to one of the memory cells is carried out, a security information stored in a security memory cell is read out. If the security...
US-6,560,731 Method for checking the functioning of memory cells of an integrated semiconductor memory
In a method for checking the functioning of memory cells of an integrated semiconductor memory, a first group of the memory cells is tested. The test results,...
US-6,560,149 Integrated semiconductor memory device
An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes...
US-6,560,136 Single-port memory cell
A single-port memory cell arrangement includes a multiplicity of single-port memory cells, each having a selection transistor and a memory transistor. The...
US-6,560,134 Memory configuration with a central connection area
A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory...
US-6,559,897 Method for random access to picture blocks in video pictures
During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient...
US-6,559,786 Circuit arrangement for conversion of an input current signal to a corresponding digital output signal
The invention provides a circuit arrangement for conversion of an input current signal (11) to a digital output signal (43). In particular, the invention relates...
US-6,559,785 Digital/analog converter
Digital/analog converter for converting a binary coded data word into an analog output signal, having a capacitor cell Matrix (9) comprising capacitor cells...
US-6,559,721 Circuit configuration with an integrated amplifier
A circuit configuration with an integrated amplifier is described. The amplifier has an output stage that is connected to a supply potential terminal and a...
US-6,559,716 Switchable operational amplifier for switched op-amp applications
A switchable operational amplifier is presented for switched op amp technology, in which the current through the pre-stage is reduced during the off phase of the...
US-6,559,547 Patterning of content areas in multilayer metalization configurations of semiconductor components
The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact...
US-6,559,503 Transistor with ESD protection
The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or...
US-6,559,069 Process for the electrochemical oxidation of a semiconductor substrate
In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a...
US-6,559,067 Method for patterning an organic antireflection layer
An antireflection coating (ARC) polymer layer is patterned by DUV (deep ultraviolet) lithography followed by an ARC open etching step and subsequent etching of...
US-6,559,005 Method for fabricating capacitor electrodes
The method according to the invention enables the roughness of an HSG surface to be substantially transferred to the surface of an electrode. The electrode...
US-6,559,003 Method of producing a ferroelectric semiconductor memory
A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to...
US-6,559,002 Rough oxide hard mask for DT surface area enhancement for DT DRAM
In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not...
US-6,558,883 Apparatus and method for patterning a semiconductor wafer
A method and apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the...
US-6,558,770 Perforated work piece, and method for producing it
A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are...
US-6,558,196 Shielding plate for pluggable electrical components
The shielding plate receives pluggable electrical components, in particular optoelectronic transceivers. The shielding plate has an at least partially ...
US-6,557,769 Smart card module, smart card with the smart card module, and method for producing the smart card module
Flip-chip bumps (solder bumps) are applied on the contact-connection points of a semiconductor chip. These bumps extend from there through a covering compound...
US-6,557,085 Circuit configuration for handling access contentions
The circuit handles access contentions in memories with a plurality of mutually independent, addressable I/O ports. There are provided two subcircuits, namely...
US-6,556,496 Semiconductor configuration with optimized refresh cycle
A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is...
US-6,556,492 System for testing fast synchronous semiconductor circuits
The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe...
US-6,556,486 Circuit configuration and method for synchronization
A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the...
US-6,556,418 Micromechanical component and process for its fabrication
A micromechanical component placed on a substrate face includes at least one cell. A counter-electrode of a cell capacitor is placed under a cavity. The...
US-6,556,164 Analog/digital converter and method for converting an analog input signal into a digital output signal
An analog-to-digital converter for successively and approximately converting an analog input signal into a digital output signal includes at least one comparator...
US-6,556,070 Current source that has a high output impedance and that can be used with low operating voltages
An electrical current source with a high output resistance has a current determining transistor and a regulating switch. The regulating switch has an amplifier...
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