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Patent # Description
US-6,638,774 Method of making resistive memory elements with reduced roughness
A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed...
US-6,637,947 Optical coupling configuration
The optic coupling system links a fiber-optics waveguide with two optoelectronic components. The components are disposed on a substrate with an interposed...
US-6,636,727 Phase locked loop system
A phase locked loop system for tuning the reception frequency of a receiver for digitally modulated received signals and analog-modulated received signals has at...
US-6,636,453 Memory circuit having a plurality of memory areas
A memory circuit has at least two memory areas each including a group of primary read amplifiers. Each of these groups can be connected via an assigned local...
US-6,636,447 Memory module, method for activating a memory cell, and method for repairing a defective memory cell
In the memory module, depending on the configuration chosen, the number of redundant memory cells which is assigned to a defective address is also adapted to the...
US-6,636,372 Accumulating read channel performance data
Systems and methods for accumulating data relating to the performance of one or more components of a read channel are described. In one aspect, a programmable...
US-6,636,097 Method and input circuit for evaluating a data signal at an input of a memory component
The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is...
US-6,636,033 Sensor apparatus and method for generating an output signal of a sensor apparatus
A sensor apparatus having a sensor for generating an analog sensor signal with successive minima and maxima is provided. The apparatus can include a first output...
US-6,635,947 Monolithically integrable inductor
A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one...
US-6,635,944 Power semiconductor component having a PN junction with a low area edge termination
Component having a blocking pn junction having an edge termination structure which is formed by a further, more weakly doped region (5) and a trench (8) formed...
US-6,635,930 Protective circuit
A protective circuit for limiting a voltage at a pad of an integrated circuit includes a threshold selector connected between the pad and ground. The input...
US-6,635,567 Method of producing alignment marks
Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are...
US-6,635,564 Semiconductor structure and method of fabrication including forming aluminum columns
High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the...
US-6,635,546 Method and manufacturing MRAM offset cells in a damascene structure
A method of manufacturing an offset MRAM device (110), including utilizing two resist layers either to pattern a magnetic stack layer to form offset conductive...
US-6,635,545 Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration...
The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar...
US-6,635,526 Structure and method for dual work function logic devices in vertical DRAM process
Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56...
US-6,635,496 Plate-through hard mask for MRAM devices
A method of fabricating an MRAM device includes patterning a magnetic stack material layer (142) using a herd mask (146) formed by a "plate-through" technique. A...
US-6,635,410 Metallizing method for dielectrics
A method for metallizing dielectrics includes applying a photosensitive dielectric to a substrate. The dielectric is then exposed to light through a mask, is...
US-6,635,388 Contact hole fabrication with the aid of mutually crossing sudden phase shift edges of a single phase shift mask
The invention relates to a phase shift mask for lithographically producing small structures at the limit of a resolution that is predetermined by the wavelength...
US-RE38,280 Optoelectronic module for bidirectional optical data transmission
An optoelectric module for bidirectional optical data transmission has a molded element provided as a beam splitter, which consists essentially of a material...
US-6,633,501 Integrated circuit and circuit configuration for supplying power to an integrated circuit
An integrated circuit for processing security-relevant data has data output circuits and access control circuits wherein a disturbance of the power supply of the...
US-6,633,447 Method and apparatus for compensation of second order distortion
A method and apparatus for removing second order distortion is disclosed. The method couples a differential load between two source followers of a gain stage....
US-6,633,379 Apparatus and method for measuring the degradation of a tool
A machining apparatus (10) comprises a material removing tool (12) movably mounted for removing material from a workpiece (14); means for illuminating (42, 54) a...
US-6,633,064 Compensation component with improved robustness
The compensation component is formed with compensation regions in a semiconductor between two electrodes. By varying the second field and/or the first field, a...
US-6,633,061 SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method
In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier...
US-6,632,687 Methods of compensating for wafer parameters
The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is...
US-6,631,511 Generating mask layout data for simulation of lithographic processes
A method for generating mask layout data for lithography simulation includes prescribing original data defining an original layout of a mask and determining a...
US-6,630,727 Modularly expandable multi-layered semiconductor component
A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one...
US-6,630,723 Laser programming of integrated circuits
Laser Programming of Integrated Circuits. The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit on a chip,...
US-6,630,703 Magnetoresistive memory cell configuration and method for its production
A storage cell configuration including magnetoresistive storage elements located in a cell field between first lines and second lines. A first metalization...
US-6,630,698 High-voltage semiconductor component
The invention relates to a high-voltage semiconductor component comprising semiconductor areas (4, 5) of alternating, different conductivity types which are...
US-6,630,379 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch
A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side...
US-6,628,860 Fiber optic connector systems
A fiber optic connector system that includes a fiber optic plug and a fiber optic socket (or input) is described. The fiber optic input includes mechanisms for...
US-6,628,553 Data output interface, in particular for semiconductor memories
A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent...
US-6,628,551 Reducing leakage current in memory cells
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage...
US-6,628,544 Flash memory cell and method to achieve multiple bits per cell
A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt...
US-6,628,541 Memory architecture with refresh and sense amplifiers
An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and...
US-6,628,467 Input/output multiplex system for a read/write channel in a disk drive
This invention provides a read/write channel with a multiplex input/output system for a disk drive, which may have one or more magnetic disks, one or more...
US-6,628,409 Method for determining the distance between periodic structures on an integrated circuit or a photomask
Fourier transformations are used to calculate a power spectrum of an image of an integrated circuit. The distance between periodic structures is determined from...
US-6,628,156 Integrated circuit having a timing circuit, and method for adjustment of an output signal from the timing circuit
An integrated circuit has a timing circuit with a power source and a capacitor. The timing circuit outputs an output signal whose time can be adjusted and which...
US-6,628,152 Method for monitoring a proper functioning of an integrated circuit
A proper functioning of an integrated circuit is monitored by monitoring a supply voltage of the integrated circuit. Dips in the supply voltage are ascertained....
US-6,628,141 Integrated circuit having a scan register chain
An integrated circuit is characterized in that circuit parts contained therein are connected to one another via an interface containing at least one scan...
US-6,627,970 Integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated...
An integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure is described. The...
US-6,627,940 Memory cell arrangement
A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of...
US-6,627,934 Integrated semiconductor memory configuration with a buried plate electrode and method for its fabrication
A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage...
US-6,627,548 Process for treating semiconductor substrates
The invention relates to a process for treating semiconductor substrates in which metal layers are exposed by removing one or more layers of the surface of a...
US-6,627,498 Memory cell fabrication method and memory cell configuration
The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a...
US-6,627,496 Process for producing structured layers, process for producing components of an integrated circuit, and process...
A process for producing structured layers on a base body, in particular a semiconductor body, includes the steps of providing a first layer, structuring the...
US-6,627,392 Method of transferring a pattern of high structure density by multiple exposure of less dense partial patterns
A pattern with small, densely packed structures is transferred from a structure carrier to an object. At least two partial patterns of less densely packed...
US-6,625,076 Circuit configuration fir evaluating the information content of a memory cell
A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a...
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