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Patent # Description
US-6,608,777 Circuit configuration for reading memory elements
A circuit configuration for measuring or calibrating current of components in memory elements, preferably, EPROM or EEPROM memory elements, includes a memory...
US-6,608,532 Circuit configuration for producing a quadrature-amplitude-modulated transmission signal
A circuit configuration for a QAM transmitter contains a Cordic for converting the baseband signal to the radio frequency band. The complex output signal from...
US-6,608,341 Trench capacitor with capacitor electrodes
A trench capacitor for use in a semiconductor memory cell is formed in a substrate. The trench capacitor includes a trench having an upper region and a lower...
US-6,608,340 Substrate assembly having a depression suitable for an integrated circuit configuration and method for its...
A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of...
US-6,607,984 Removable inorganic anti-reflection coating process
In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first...
US-6,607,972 Method for producing an edge termination suitable for high voltages in a basic material wafer prefabricated...
An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in...
US-6,607,309 Optical device
An optical device includes a surface-mountable optical component with a base member having a recess filled with a transparent filler and a VCSEL element arranged...
US-6,606,445 Method for producing a holding configuration for at least one sheathed optical fiber conductor
A method for producing a holding configuration for at least one sheathed optical fiber conductor, which includes forming a holding body with a through-channel...
US-6,606,151 Grating patterns and method for determination of azimuthal and radial aberration
Methods and reticles for evaluating lenses are disclosed. In one instance, a reticle which permits light to pass therethrough is provided which includes a first...
US-6,606,008 Oscillator circuit
An oscillator circuit is described and has an oscillator core with at least one inductance and, connected thereto, a first and second capacitance. A deattenuator...
US-6,605,987 Circuit for generating a reference voltage based on two partial currents with opposite temperature dependence
A circuit for generating a temperature-stabilized reference voltage uses the current-mode technique, in which two partial currents are superimposed on each other...
US-6,605,927 Circuit configuration for discharging a capacitor which has been charged to a high voltage to a low voltage...
The object is to discharge a first capacitor from a high voltage to a low voltage. To this end, the one electrode of the first capacitor is linked with the one...
US-6,605,864 Support matrix for integrated semiconductors, and method for producing it
Support matrices for semiconductors are often disposed with spacers on the semiconductor chip. The spacers are composed of silicone that flows into the region of...
US-6,605,860 Semiconductor structures and manufacturing methods
A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a...
US-6,605,841 Method for producing an electrode by means of a field effect controllable semiconductor component and...
A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone...
US-6,605,838 Process flow for thick isolation collar with reduced length
A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic...
US-6,605,837 Memory cell configuration and production method
A memory cell configuration includes a magnetoresistive element with an annular cross-section in a layer plane, a first line and a second line. The first and...
US-6,605,504 Method of manufacturing circuit with buried strap including a liner
Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such...
US-6,605,487 Method for the manufacture of micro-mechanical components
A method for the manufacture of micro-mechanical components from a stack of layers having at least a substrate, a sacrificial layer and a layer which is to be...
US-6,605,396 Resolution enhancement for alternating phase shift masks
An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist...
US-6,604,862 Multichannel optical coupling configuration
A coupling system includes an optical plug-in connector, a coupling partner and a retaining element. The housing of the plug-in connector is provided with a...
US-6,603,699 Configuration for fuse initialization
The invention relates to a configuration for fuse initialization, in which the fuse initialization signals bFPUP, FPUN are carried on a total of two lines to the...
US-6,603,694 Dynamic memory refresh circuitry
A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of...
US-6,603,344 Zero static power programmable fuse cell for integrated circuits
A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell includes programmable and...
US-6,603,170 Integrated semiconductor configuration having a semiconductor memory with user programmable bit width
An integrated semiconductor circuit is described and has a semiconductor memory configuration embedded in a semiconductor chip and an interface circuit. The...
US-6,603,164 Integrated semiconductor memory configuration
The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be...
US-6,602,788 Process for fabricating an interconnect for contact holes
A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning...
US-6,602,745 Field effect transistor and method of fabrication
An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a...
US-6,602,729 Pulse voltage breakdown (VBD) technique for inline gate oxide reliability monitoring
Disclosed is a method of testing a dielectric, comprising setting a reference current below a breakdown current of the dielectric, applying a stress voltage to...
US-6,602,127 Plant for producing semiconductor products
A plant for producing semiconductor products that includes at least one clean room having a floor and a plurality of production units that are configured in the...
US-6,602,123 Finishing pad design for multidirectional use
A polishing pad (for example, polishing pad 305) for use in polarization of a semiconductor wafer (for example, semiconductor wafer 420), the polishing pad 305...
US-6,601,205 Method to descramble the data mapping in memory circuits
An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards...
US-6,601,202 Circuit configuration with deactivatable scan path
A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At...
US-6,601,194 Circuit configuration for repairing a semiconductor memory
A semiconductor memory of an integrated circuit has memory cells that are combined to form individually addressable normal units and redundant units for...
US-6,600,912 Receiver for various frequency bands
The receiver for various frequency bands has only one oscillator (OSZ), which is followed downstream by a frequency divider having a settable real divisor value....
US-6,600,680 Circuit configuration and method for determining a time constant of a storage capacitor of a memory cell in a...
A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its...
US-6,600,615 Synchronous timing for interpolated timing recovery
Synchronous acquisition in a sampled amplitude read channel. A timing error estimation unit (302) is provided to calculate an acquisition timing error. The...
US-6,600,433 Method and apparatus for correcting digital code words in a digital communication network
Digital code words are transmitted via a digital communication network, e.g. from a digital modem (1) to an analog modem (5). Whenever an RBS technique is used...
US-6,600,366 Differential line driver circuit
Differential line driver circuit for driving a line signal output via a signal line.
US-6,600,331 Method and device for measuring a temperature in an electronic component
The invention relates to a method for measuring the junction temperature in an electronic component. A periodic test signal is led via a signal path inside the...
US-6,600,200 MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS...
A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial...
US-6,599,843 In-situ mask technique for producing III-V semiconductor components
Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one...
US-6,599,798 Method of preparing buried LOCOS collar in trench DRAMS
The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of...
US-6,599,797 SOI DRAM without floating body effect
The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO.sub.2 layer (O). An upper part of said...
US-6,599,033 Device for sealing a coupling unit for an optoelectronic component against contaminants
A device for sealing a coupling unit for an optoelectronic component against contaminants includes a sealing element having at least one open end to be...
US-6,598,034 Rule based IP data processing
A apparatus and method that provides a routing engine for processing data packets based upon certain rules that are compiled and applied real-time via a...
US-6,597,945 Method for detecting living human skin
A characteristic curve of the impedance of a skin surface is measured as a function of the frequency of an electric AC voltage by applying the voltage to at...
US-6,597,200 Circuit arrangement for scalable output drivers
The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups being provided which each have...
US-6,596,625 Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit
Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer...
US-6,596,580 Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure
The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited...
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