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Patent # Description
US-6,599,033 Device for sealing a coupling unit for an optoelectronic component against contaminants
A device for sealing a coupling unit for an optoelectronic component against contaminants includes a sealing element having at least one open end to be...
US-6,598,034 Rule based IP data processing
A apparatus and method that provides a routing engine for processing data packets based upon certain rules that are compiled and applied real-time via a...
US-6,597,945 Method for detecting living human skin
A characteristic curve of the impedance of a skin surface is measured as a function of the frequency of an electric AC voltage by applying the voltage to at...
US-6,597,200 Circuit arrangement for scalable output drivers
The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups being provided which each have...
US-6,596,625 Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit
Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer...
US-6,596,580 Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure
The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited...
US-6,594,546 Plant for processing wafers
A plant for processing wafers, having a plurality of fabrication units, a plurality of measuring units, and a transport system for transporting the wafers. The...
US-6,594,300 Vertical-resonator-laser-diode with a light-absorbing layer and method of manufacturing the same
A vertical-resonator-laser-diode and a method of manufacturing the same are disclosed. An active layer sequence for the production of laser-radiation is...
US-6,594,191 Segmented write line architecture
This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a...
US-6,594,188 Integrated memory having a cell array and charge equalization devices, and method for the accelerated writing...
An integrated memory having a memory cell array with addressable column lines and addressable row lines is described. The memory further has a charge...
US-6,594,176 Current source and drain arrangement for magnetoresistive memories (MRAMs)
An MRAM device (400) having write paths with substantially uniform length and resistance for all memory cells within the memory array (411). CVC circuits are...
US-6,594,094 Read/write channel
An improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel...
US-6,593,868 Differential digital/analog converter
A differential digital/analog converter for the conversion of a digital input value into an analog output voltage with a first current source group, which has a...
US-6,593,814 Amplifier circuit with protective device
An amplifier circuit having an amplifier stage is specified, in which, in order to avoid breakdown effects in the transistors thereof, an in-phase regulator is...
US-6,593,763 Module test socket for test adapters
A module test socket is described in which a memory module and a terminal board are disposed vertically in relation to each other in one plane. A first row of...
US-6,593,614 Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it
A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive...
US-6,593,613 Memory cell for plateline sensing
Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the...
US-6,593,612 Structure and method for forming a body contact for vertical transistor cells
A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a...
US-6,593,254 Method for clamping a semiconductor device in a manufacturing process
There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least...
US-6,593,242 Process for planarization and recess etching of integrated circuits
The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the...
US-6,593,240 Two step chemical mechanical polishing process
A method for polishing a semiconductor wafer includes providing a semiconductor wafer having topographical features and forming a dielectric layer on the...
US-6,593,228 Method of fabricating a patterned metal-containing layer on a semiconductor wafer
A metal-containing layer is formed on a substrate. A mask layer is formed on the metal-containing layer. The mask layer is patterned by way of a lithographically...
US-RE38,184 Circuit for displaying operating states of a device
A circuit receives at least two input signals and produces exactly three output signals in response to the two input signals, whereby two of the output signals...
US-6,591,034 Configuration for spatially separating and/or joining optical wavelength channels
A configuration for spatially separating and/or joining at least two optical wavelength channels includes an optical phased array device which has a device for...
US-6,590,824 Dynamic semiconductor memory with refresh and method for operating such a memory
A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with...
US-6,590,821 Memory device
A description is given of a memory device having memory cells for storing data. The memory device described is distinguished by the fact that a current...
US-6,590,816 Integrated memory and method for testing and repairing the integrated memory
The integrated memory has memory cells in a memory cell block having a plurality of column lines and a plurality of row lines. The row lines include regular row...
US-6,590,657 Semiconductor structures and manufacturing methods
A semiconductor body having an alignment mark comprising a material adapted to absorb impinging light and to radiate light in response to the absorption of the...
US-6,590,457 Phase detector and clock regeneration device
A phase detector device and a clock regeneration device for phase centering when incoming data are sampled at a clock rate, which is in particular substantially...
US-6,590,384 Method of communicating with a built-in sensor, in particular a rotational speed sensor
The method allows communication with a built-in sensor, in particular a rotational speed sensor, which supplies successive signal pulses as output signal. The...
US-6,590,263 ESD protection configuration for signal inputs and outputs in semiconductor devices with substrate isolation
In the ESD protection configuration, in addition to the existing protection configurations, at each supply pad of the supply bus, an ESD diode is also inserted...
US-6,590,249 One-transistor memory cell configuration and method for its fabrication
In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor...
US-6,589,832 Spacer formation in a deep trench memory cell
In a process for manufacturing deep trench memory cells, a method of forming a nitride spacer so as to avoid shorts resulting from poly filling voids in said...
US-6,587,894 Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time...
According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed....
US-6,587,544 Method for measuring a load impedance
Method for measuring a load impedance (Z.sub.L) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal...
US-6,587,524 Reception method and receiver for mobile radiotelephone applications
In a receiving method for mobile radio applications, a given user data signal and at least one further user data signal located within the same frequency band...
US-6,587,489 Electronic driver circuit for directly modulated semiconductor lasers
An electronic driver circuit for directly modulated semiconductor lasers is described. The drive circuit has a first circuit for generating a constant current...
US-6,587,361 Switched-mode power supply with low switching losses
A method for driving a switch in a switched-mode power supply, in which the switch is connected in series with a primary coil of a transformer and in which a...
US-6,587,292 Magneto-resistive asymmetry compensation loop
A magneto-resistive asymmetry compensation system includes a linearizer (61) interposed in a data path and a control loop (63). The control loop uses signal...
US-6,586,978 Delay locked loop
A delay locked loop has a filter in order to set the delay time of a delay path in a manner dependent on the phase difference of input and output clock signals....
US-6,586,960 Measuring device for testing unpacked chips
A measuring device has a needle-board circuit board carrying a large number of contact-making needles for contacting connecting areas on an IC circuit. The...
US-6,586,919 Voltage-current converter
The invention concerns a voltage-current converter having: a first current mirror containing two transistors that are designed such that under identical drive...
US-6,586,795 DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties
Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the...
US-6,586,348 Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation...
After an SBT layer is precipitated onto a substrate, the SBT layer is structured as a still amorphous layer. Only subsequently is it subjected to a...
US-6,586,308 Method for producing circuit structures on a semiconductor substrate and semiconductor configuration with...
A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit...
US-6,586,305 Method for producing transistors in integrated semiconductor circuits
Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel...
US-6,586,300 Spacer assisted trench top isolation for vertical DRAM's
A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133)...
US-6,584,681 Method for producing a microelectronic component of sandwich construction
A method for producing a microelectronic component of sandwich construction, which includes the steps of providing a first substrate which has a first conductor...
US-6,584,087 Power control during inter-generation soft handoffs
A method for power control during soft handoffs is disclosed for a multi-user CDMA system having mixed system types, such as IS-95A/B and IS-2000. The procedure...
US-6,584,021 Semiconductor memory having a delay locked loop
A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output...
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