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Differential digital/analog converter
A differential digital/analog converter for the conversion of a digital input value into an analog output voltage with a first current source group, which has a...
Amplifier circuit with protective device
An amplifier circuit having an amplifier stage is specified, in which, in order to avoid breakdown effects in the transistors thereof, an in-phase regulator is...
Module test socket for test adapters
A module test socket is described in which a memory module and a terminal board are disposed vertically in relation to each other in one plane. A first row of...
Integrated circuit configuration having at least one transistor and one
capacitor, and method for fabricating it
A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive...
Memory cell for plateline sensing
Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the...
Structure and method for forming a body contact for vertical transistor
A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a...
Method for clamping a semiconductor device in a manufacturing process
There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least...
Process for planarization and recess etching of integrated circuits
The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the...
Two step chemical mechanical polishing process
A method for polishing a semiconductor wafer includes providing a semiconductor wafer having topographical features and forming a dielectric layer on the...
Method of fabricating a patterned metal-containing layer on a semiconductor
A metal-containing layer is formed on a substrate. A mask layer is formed on the metal-containing layer. The mask layer is patterned by way of a lithographically...
Circuit for displaying operating states of a device
A circuit receives at least two input signals and produces exactly three output signals in response to the two input signals, whereby two of the output signals...
Configuration for spatially separating and/or joining optical wavelength
A configuration for spatially separating and/or joining at least two optical wavelength channels includes an optical phased array device which has a device for...
Dynamic semiconductor memory with refresh and method for operating such a
A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with...
A description is given of a memory device having memory cells for storing data. The memory device described is distinguished by the fact that a current...
Integrated memory and method for testing and repairing the integrated
The integrated memory has memory cells in a memory cell block having a plurality of column lines and a plurality of row lines. The row lines include regular row...
Semiconductor structures and manufacturing methods
A semiconductor body having an alignment mark comprising a material adapted to absorb impinging light and to radiate light in response to the absorption of the...
Phase detector and clock regeneration device
A phase detector device and a clock regeneration device for phase centering when incoming data are sampled at a clock rate, which is in particular substantially...
Method of communicating with a built-in sensor, in particular a rotational
The method allows communication with a built-in sensor, in particular a rotational speed sensor, which supplies successive signal pulses as output signal. The...
ESD protection configuration for signal inputs and outputs in semiconductor
devices with substrate isolation
In the ESD protection configuration, in addition to the existing protection configurations, at each supply pad of the supply bus, an ESD diode is also inserted...
One-transistor memory cell configuration and method for its fabrication
In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor...
Spacer formation in a deep trench memory cell
In a process for manufacturing deep trench memory cells, a method of forming a nitride spacer so as to avoid shorts resulting from poly filling voids in said...
Apparatus for detecting data collision on data bus for out-of-order memory
accesses with access execution time...
According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed....
Method for measuring a load impedance
Method for measuring a load impedance (Z.sub.L) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal...
Reception method and receiver for mobile radiotelephone applications
In a receiving method for mobile radio applications, a given user data signal and at least one further user data signal located within the same frequency band...
Electronic driver circuit for directly modulated semiconductor lasers
An electronic driver circuit for directly modulated semiconductor lasers is described. The drive circuit has a first circuit for generating a constant current...
Switched-mode power supply with low switching losses
A method for driving a switch in a switched-mode power supply, in which the switch is connected in series with a primary coil of a transformer and in which a...
Magneto-resistive asymmetry compensation loop
A magneto-resistive asymmetry compensation system includes a linearizer (61) interposed in a data path and a control loop (63). The control loop uses signal...
Delay locked loop
A delay locked loop has a filter in order to set the delay time of a delay path in a manner dependent on the phase difference of input and output clock signals....
Measuring device for testing unpacked chips
A measuring device has a needle-board circuit board carrying a large number of contact-making needles for contacting connecting areas on an IC circuit. The...
The invention concerns a voltage-current converter having: a first current mirror containing two transistors that are designed such that under identical drive...
DRAM cell configuration whose memory cells can have transistors and
capacitors with improved electrical properties
Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the...
Method for preventing etching-induced damage to a metal oxide film by
patterning the film after a nucleation...
After an SBT layer is precipitated onto a substrate, the SBT layer is structured as a still amorphous layer. Only subsequently is it subjected to a...
Method for producing circuit structures on a semiconductor substrate and
semiconductor configuration with...
A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit...
Method for producing transistors in integrated semiconductor circuits
Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel...
Spacer assisted trench top isolation for vertical DRAM's
A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133)...
Method for producing a microelectronic component of sandwich construction
A method for producing a microelectronic component of sandwich construction, which includes the steps of providing a first substrate which has a first conductor...
Power control during inter-generation soft handoffs
A method for power control during soft handoffs is disclosed for a multi-user CDMA system having mixed system types, such as IS-95A/B and IS-2000. The procedure...
Semiconductor memory having a delay locked loop
A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output...
Memory integrated circuit with improved reliability
A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first...
MRAM bit line word line architecture
A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the ...
Device and method for compensating for propagation delay
The device and method compensate for propagation differences between n serial data streams each transmitted over parallel optical lines. Data that can be...
Stability enhanced multistage power amplifier
A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage...
Active auto zero circuit for time continuous open loop amplifiers
An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal...
Integrated circuit with active regions having varying contact arrangements
The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S1, D1, S2, D2, S3) arranged in parallel next to one...
Memory cell using amorphous material to stabilize the boundary face between
A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a...
Method for fabricating a trench isolation for electrically active
A method for fabricating a trench isolation for electrically active components in a semiconductor component. A mask is applied to a semiconductor substrate....
Data carrier with regulation of the power consumption
A data carrier, in particular a smart card, is described and has at least one transmitting/receiving antenna and also a rectifier circuit connected downstream...
Circuit configuration for the burn-in test of a semiconductor module
A circuit for the burn-in test of a semiconductor module, to which burn-in test signals from a burn-in test device can be applied, has memory elements. Each...
Method and configuration for comparing a first characteristic with
predetermined characteristics of a technical...
The objective of the invention is to detect a characteristic in a technical system with reference to model checking. A comparison is made, involving the...
System and method for finding an operation/tool combination that causes
integrated failure in a semiconductor...
A system and method for finding operation/tool's combination which causes the integration failure in a semiconductor fabrication facility is disclosed. It...