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Circuit configuration with deactivatable scan path
A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At...
Circuit configuration for repairing a semiconductor memory
A semiconductor memory of an integrated circuit has memory cells that are combined to form individually addressable normal units and redundant units for...
Receiver for various frequency bands
The receiver for various frequency bands has only one oscillator (OSZ), which is followed downstream by a frequency divider having a settable real divisor value....
Circuit configuration and method for determining a time constant of a
storage capacitor of a memory cell in a...
A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its...
Synchronous timing for interpolated timing recovery
Synchronous acquisition in a sampled amplitude read channel. A timing error estimation unit (302) is provided to calculate an acquisition timing error. The...
Method and apparatus for correcting digital code words in a digital
Digital code words are transmitted via a digital communication network, e.g. from a digital modem (1) to an analog modem (5). Whenever an RBS technique is used...
Differential line driver circuit
Differential line driver circuit for driving a line signal output via a signal line.
Method and device for measuring a temperature in an electronic component
The invention relates to a method for measuring the junction temperature in an electronic component. A periodic test signal is led via a signal path inside the...
MOS transistor, method for fabricating a MOS transistor and method for
fabricating two complementary MOS...
A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial...
In-situ mask technique for producing III-V semiconductor components
Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one...
Method of preparing buried LOCOS collar in trench DRAMS
The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of...
SOI DRAM without floating body effect
The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO.sub.2 layer (O). An upper part of said...
Device for sealing a coupling unit for an optoelectronic component against
A device for sealing a coupling unit for an optoelectronic component against contaminants includes a sealing element having at least one open end to be...
Rule based IP data processing
A apparatus and method that provides a routing engine for processing data packets based upon certain rules that are compiled and applied real-time via a...
Method for detecting living human skin
A characteristic curve of the impedance of a skin surface is measured as a function of the frequency of an electric AC voltage by applying the voltage to at...
Circuit arrangement for scalable output drivers
The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups being provided which each have...
Method and device for producing a metal/metal contact in a multilayer
metallization of an integrated circuit
Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer...
Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the
method to form this structure
The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited...
Plant for processing wafers
A plant for processing wafers, having a plurality of fabrication units, a plurality of measuring units, and a transport system for transporting the wafers. The...
Vertical-resonator-laser-diode with a light-absorbing layer and method of
manufacturing the same
A vertical-resonator-laser-diode and a method of manufacturing the same are disclosed. An active layer sequence for the production of laser-radiation is...
Segmented write line architecture
This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a...
Integrated memory having a cell array and charge equalization devices, and
method for the accelerated writing...
An integrated memory having a memory cell array with addressable column lines and addressable row lines is described. The memory further has a charge...
Current source and drain arrangement for magnetoresistive memories (MRAMs)
An MRAM device (400) having write paths with substantially uniform length and resistance for all memory cells within the memory array (411). CVC circuits are...
An improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel...
Differential digital/analog converter
A differential digital/analog converter for the conversion of a digital input value into an analog output voltage with a first current source group, which has a...
Amplifier circuit with protective device
An amplifier circuit having an amplifier stage is specified, in which, in order to avoid breakdown effects in the transistors thereof, an in-phase regulator is...
Module test socket for test adapters
A module test socket is described in which a memory module and a terminal board are disposed vertically in relation to each other in one plane. A first row of...
Integrated circuit configuration having at least one transistor and one
capacitor, and method for fabricating it
A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive...
Memory cell for plateline sensing
Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the...
Structure and method for forming a body contact for vertical transistor
A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a...
Method for clamping a semiconductor device in a manufacturing process
There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least...
Process for planarization and recess etching of integrated circuits
The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the...
Two step chemical mechanical polishing process
A method for polishing a semiconductor wafer includes providing a semiconductor wafer having topographical features and forming a dielectric layer on the...
Method of fabricating a patterned metal-containing layer on a semiconductor
A metal-containing layer is formed on a substrate. A mask layer is formed on the metal-containing layer. The mask layer is patterned by way of a lithographically...
Circuit for displaying operating states of a device
A circuit receives at least two input signals and produces exactly three output signals in response to the two input signals, whereby two of the output signals...
Configuration for spatially separating and/or joining optical wavelength
A configuration for spatially separating and/or joining at least two optical wavelength channels includes an optical phased array device which has a device for...
Dynamic semiconductor memory with refresh and method for operating such a
A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with...
A description is given of a memory device having memory cells for storing data. The memory device described is distinguished by the fact that a current...
Integrated memory and method for testing and repairing the integrated
The integrated memory has memory cells in a memory cell block having a plurality of column lines and a plurality of row lines. The row lines include regular row...
Semiconductor structures and manufacturing methods
A semiconductor body having an alignment mark comprising a material adapted to absorb impinging light and to radiate light in response to the absorption of the...
Phase detector and clock regeneration device
A phase detector device and a clock regeneration device for phase centering when incoming data are sampled at a clock rate, which is in particular substantially...
Method of communicating with a built-in sensor, in particular a rotational
The method allows communication with a built-in sensor, in particular a rotational speed sensor, which supplies successive signal pulses as output signal. The...
ESD protection configuration for signal inputs and outputs in semiconductor
devices with substrate isolation
In the ESD protection configuration, in addition to the existing protection configurations, at each supply pad of the supply bus, an ESD diode is also inserted...
One-transistor memory cell configuration and method for its fabrication
In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor...
Spacer formation in a deep trench memory cell
In a process for manufacturing deep trench memory cells, a method of forming a nitride spacer so as to avoid shorts resulting from poly filling voids in said...
Apparatus for detecting data collision on data bus for out-of-order memory
accesses with access execution time...
According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed....
Method for measuring a load impedance
Method for measuring a load impedance (Z.sub.L) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal...
Reception method and receiver for mobile radiotelephone applications
In a receiving method for mobile radio applications, a given user data signal and at least one further user data signal located within the same frequency band...
Electronic driver circuit for directly modulated semiconductor lasers
An electronic driver circuit for directly modulated semiconductor lasers is described. The drive circuit has a first circuit for generating a constant current...
Switched-mode power supply with low switching losses
A method for driving a switch in a switched-mode power supply, in which the switch is connected in series with a primary coil of a transformer and in which a...