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Method for monitoring a proper functioning of an integrated circuit
A proper functioning of an integrated circuit is monitored by monitoring a supply voltage of the integrated circuit. Dips in the supply voltage are ascertained....
Integrated circuit having a scan register chain
An integrated circuit is characterized in that circuit parts contained therein are connected to one another via an interface containing at least one scan...
Integrated semiconductor circuit, in particular a semiconductor memory
circuit, having at least one integrated...
An integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure is described. The...
Memory cell arrangement
A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of...
Integrated semiconductor memory configuration with a buried plate electrode
and method for its fabrication
A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage...
Process for treating semiconductor substrates
The invention relates to a process for treating semiconductor substrates in which metal layers are exposed by removing one or more layers of the surface of a...
Memory cell fabrication method and memory cell configuration
The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a...
Process for producing structured layers, process for producing components
of an integrated circuit, and process...
A process for producing structured layers on a base body, in particular a semiconductor body, includes the steps of providing a first layer, structuring the...
Method of transferring a pattern of high structure density by multiple
exposure of less dense partial patterns
A pattern with small, densely packed structures is transferred from a structure carrier to an object. At least two partial patterns of less densely packed...
Circuit configuration fir evaluating the information content of a memory
A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a...
Method for masking DQ bits
A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided...
Wafer supporting plate
A wafer supporting plate suitable for supporting a wafer during a semiconductor-forming process. In particular, the present invention relates to a wafer...
System for programming fuse structure by electromigration of silicide
enhanced by creating temperature gradient
The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode...
The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and...
Fabrication process for a semiconductor component
A process for fabricating a semiconductor component includes providing a trench in a substrate and depositing a liner layer on the resulting structure using a...
Plant for producing semiconductor products
A plant for producing semiconductor products is described and has a plurality of production and measuring units in at least one clean room. Provided there is a...
Electro-optical data transfer module
An electro-optical data transmission module comprises at least a first SMT housing (11) and a second SMT housing (13). A surface-emitting laser light emitter...
Timing device and timing method
A timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. The timing device includes a...
Refreshing scheme for memory cells a memory array to increase performance
of integrated circuits
In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed...
Memory cells with improved reliability
A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A...
Analog-to-digital converter circuit
An analog-to-digital converter circuit including an analog-to-digital converter and calibrating circuit, preferably in the form of a digital logic, for the...
Voltage-controlled oscillator for frequency modulation
A voltage-controlled oscillator for frequency modulation includes an oscillator core with a tunable resonant circuit component which is driven with a control...
Phase-locked loop with short transient recovery duration and small
interference signal component
In order to shorten the transient recovery duration, the phase-locked loop has a voltage-controlled oscillator providing an oscillator signal to a first...
Open loop variable gain amplifier using replica gain cell
A variable gain amplifier ("VGA") having an open loop architecture is disclosed. The VGA includes one or more gain cells coupled in the signal path to amplify a...
Frequency-compensated, multistage amplifier configuration and method for
operating a frequency-compensated...
A frequency compensation circuit includes a first and a second compensation capacitor for a frequency-compensated amplifier to which a chopped useful signal can...
Clocking and synchronization circuitry
A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A...
DRAM with vertical transistor and trench capacitor memory cells and methods
A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A...
Low resistivity deep trench fill for DRAM and EDRAM applications
Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor...
Method of fabricating a metal-insulator-metal (MIM) capacitor
A method of manufacturing a metal-insulator-metal capacitor (MIMCap) (36) including first conductive lines (15), capacitor dielectric (26) and second conductive...
Method for forming inside nitride spacer for deep trench device DRAM cell
A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched...
Support liner for isolation trench height control in vertical DRAM
A method of manufacturing a vertical DRAM device (10) having isolation trenches (38) with a controlled height. A support liner (54) is disposed over support...
Method for producing a semiconductor component with a silicon carrier
Semiconductor chips are mounted on a multilayer wiring of a silicon carrier substrate, while the bottom side of the carrier substrate is provided with soldering...
Photomask, method of lithographically structuring a photoresist layer with
the photomask, and method of...
The photomask and the associated method of lithography and mask technique enable production of a regular configuration of resist dots or holes. At least one...
Configuration and method for producing test signals for testing a
multiplicity of semiconductor chips
A configuration for producing test signals for testing semiconductor chips includes a clock signal source for producing a clock signal, and a tester. The test...
Process for monitoring processing plants
A method of monitoring and/or controlling machining plans having time-dependent machining parameters includes measuring desired time-dependent machining...
Method for improving acoustic sidetone suppression in hands-free telephones
A method for improving acoustic sidetone suppression in hands-free telephones, in particular for use in motor vehicles, is described. The telephone has a level...
Optoelectronic semiconductor component
An Optoelectronic semiconductor component, in which an active zone is disposed above a semiconductor substrate, and which zone is disposed between at least one...
Semiconductor memory device having row and column redundancy circuit and
method of manufacturing the circuit
A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing...
Test circuit for testing a circuit
Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are...
Integrated circuit, test structure and method for testing integrated
An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only...
Electrical antifuse with external capacitance
An antifuse having a dielectric disposed between a plurality of conductive elements is programmed with one of the conductive elements connected to a capacitor....
Ultra high speed clocked analog latch
An ultra high-speed clocked analog latch is revealed for use at clock speeds from 100 MHz to several GHz. The analog latch is used as a latching comparator for...
Field-effect-controllable semiconductor configuration with a laterally
extending channel zone
A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first...
Nonvolatile memory cell and method for producing the memory cell
An EPROM-like memory includes a substrate having a source region, a drain region, and a channel. The memory includes a gate stack formed by a gate oxide, a...
Method for achieving high self-aligning vertical gate studs relative to the
support isolation level
A vertical gate transistor has a gate stud (14) that extends above the substrate (20) surface in order to contact a word line. The stud is formed of a first...
Method for checking the authenticity of a data medium
In a method for checking the authenticity of a data medium, in particular a smart card, the encrypted form of a physical feature of the data medium is stored in...
System and method for tracking selectively enabling modules used in an
integrated processor using a tracking...
An integrated processor is provided having functional unit tracking and monitoring capabilities. The processor core is configured to read configuration data and...
Semiconductor chip configuration and method of controlling a semiconductor
An integrated semiconductor chip is connected to external terminals with all of its data-carrying bonding pads. One of a plurality of possible data input/data...
Module for optical signal transmission
The module for optical signal transmission has a transmitting or receiving component mounted on a carrier. At least one optical waveguide, whose two ends...
FIR filter architecture for 100Base-TX receiver
A 100Base-TX receiver employs a finite impulse response (FIR) filter to provide both equalization and insertion loss compensation for an MLT-3 input signal. The...