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Patent # Description
US-6,646,299 Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated...
A first capacitor electrode and at least part of a second capacitor electrode of a capacitor are produced in depressions of an auxiliary layer by electroplating....
US-6,646,294 Circuit configuration with a plurality of transistors of two different conductivity types
The circuit configuration, in particular a logic or digital circuit, has transistors of different conductivity types. The transistors are disposed in...
US-6,646,260 Measurement technique for determining the width of a structure on a mask
A measurement technique for determining the width of a structure on a mask is described. During a focus sweep, the width of the structure on a photomask, and an...
US-6,645,855 Method for fabricating an integrated semiconductor product
A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next...
US-6,645,850 Semiconductor device having cavities with submicrometer dimensions generated by a swelling process
A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a...
US-6,645,839 Method for improving a doping profile for gas phase doping
A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon...
US-6,645,822 Method for manufacturing a semiconductor circuit system
To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a...
US-6,645,812 Method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window
A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late...
US-6,645,809 Process for producing a capacitor configuration
In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct...
US-6,645,683 Control system and methods for photolithographic processes
In the control method for photolithographic processes, line width errors and/or positional errors measured on processed semiconductor wafers are used to...
US-6,643,559 Method for monitoring a semiconductor fabrication process for processing a substrate
The invention relates to a method for monitoring a production process, whereby several models are used for detecting a finish point. The results of the model are...
US-6,643,558 Installation for processing wafers
The wafer processing installation is disposed in one or more clean rooms. The installation has a configuration of processing units including fabrication units...
US-6,643,344 Tracking method and configuration for carrying out the method
A method for tracking a locally generated spread spectrum signal sequence includes the step of correcting the spread spectrum signal sequences with respect to...
US-6,643,301 Control device for laser diodes
A device for adjusting laser diodes includes a pilot signal adjustment device for adjusting the signal current using a pilot signal frequency that is modulated...
US-6,643,211 Integrated memory having a plurality of memory cell arrays
What is specified is an integrated memory having a plurality of memory cell arrays that are each assigned row decoders and column decoders. During read or write...
US-6,643,198 RAM circuit with redundant word lines
A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is...
US-6,643,144 Circuit configuration for applying a supply voltage to a load and method for such application
A circuit configuration for pulsed application of a first supply voltage to a load includes a first switch, connected in series with the load, a first control...
US-6,642,880 Tunable analog to digital converter
A tunable analog-to-digital converter which generates samples having M-bits for use with an operating circuit. The operating circuit generates a first enable...
US-6,642,804 Oscillator circuit
The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C') which...
US-6,642,790 Differential, complementary amplifier
A differential amplifier has two amplifier paths. The second amplifier path is operated in the opposite direction relative to the first amplifier path. The...
US-6,642,606 Method for producing siliconized polysilicon contacts in integrated semiconductor structures
In the manufacture of integrated semiconductor structures, the problem frequently occurs that the resistance of polysilicon structures employed as interconnects...
US-6,642,602 Self-terminating blow process of electrical anti-fuses
An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18)....
US-6,642,565 Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G....
A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface...
US-6,641,416 Mounting holder
The holder is suitable for detachably fixing a component in an operational end position. The holder has an upper side on which the component is moved into the...
US-6,639,958 Circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock
The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for...
US-6,639,937 Method and apparatus for producing spread-coded signals
Transmission data that will be transmitted is coded and thus band-spread using a spread code. The band-spread transmission data is also coded using a scrambling...
US-6,639,862 Semiconductor memory with refresh and method for operating the semiconductor memory
To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal...
US-6,639,861 Integrated memory and method for testing an integrated memory
An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to...
US-6,639,856 Memory chip having a test mode and method for checking memory cells of a repaired memory chip
The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a...
US-6,639,846 Method and circuit configuration for a memory for reducing parasitic coupling capacitances
A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two...
US-6,639,829 Configuration and method for the low-loss writing of an MRAM
A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells...
US-6,639,825 Data memory
The data memory device has a plurality of memory cells for storing data which are represented by a first physical value of the storing memory elements,...
US-6,639,824 Memory architecture
An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage...
US-6,639,456 Current mirror and method for operating a current mirror
A current mirror and method for operating such a mirror include nonlinearly converting an input current (I.sub.in.sup.+ =I.sub.0 and, respectively, ...
US-6,639,435 Adjustable frequency divider
The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the...
US-6,639,388 Free wheeling buck regulator with floating body zone switch
A voltage transformer includes a pair of input terminals for applying an input voltage, a series circuit connected in parallel to the pair of input terminals of...
US-6,639,272 Charge compensation semiconductor configuration
Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric...
US-6,639,269 Electrically programmable memory cell configuration and method for fabricating it
A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the...
US-6,639,252 Integrated circuit and method for fabricating an integrated circuit
An integrated circuit includes a first circuit section and a second circuit section, which is necessary or useful for the emulation of the first circuit section....
US-6,638,870 Forming a structure on a wafer
A method for fabricating a structure on an integrated circuit (IC) wafer, includes providing a material onto a surface of the wafer and shaping the material to...
US-6,638,851 Dual hardmask single damascene integration scheme in an organic low k ILD
Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD)...
US-6,638,814 Method for producing an insulation
A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an...
US-6,638,812 Method for producing a memory cell for a semiconductor memory
The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole,...
US-6,638,774 Method of making resistive memory elements with reduced roughness
A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed...
US-6,637,947 Optical coupling configuration
The optic coupling system links a fiber-optics waveguide with two optoelectronic components. The components are disposed on a substrate with an interposed...
US-6,636,727 Phase locked loop system
A phase locked loop system for tuning the reception frequency of a receiver for digitally modulated received signals and analog-modulated received signals has at...
US-6,636,453 Memory circuit having a plurality of memory areas
A memory circuit has at least two memory areas each including a group of primary read amplifiers. Each of these groups can be connected via an assigned local...
US-6,636,447 Memory module, method for activating a memory cell, and method for repairing a defective memory cell
In the memory module, depending on the configuration chosen, the number of redundant memory cells which is assigned to a defective address is also adapted to the...
US-6,636,372 Accumulating read channel performance data
Systems and methods for accumulating data relating to the performance of one or more components of a read channel are described. In one aspect, a programmable...
US-6,636,097 Method and input circuit for evaluating a data signal at an input of a memory component
The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is...
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