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Patent # Description
US-6,670,668 Microelectronic structure, method for fabricating it and its use in a memory cell
A microelectronic structure that is suitable, in particular, as part of a storage capacitor includes a semiconductor structure, a barrier structure, an electrode...
US-6,670,665 Memory module with improved electrical properties
A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of...
US-6,670,662 Semiconductor storage component with storage cells, logic areas and filling structures
The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions...
US-6,670,661 Ferroelectric memory cell with diode structure to protect the ferroelectric during read operations
A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between...
US-6,670,646 Mask and method for patterning a semiconductor wafer
A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122)....
US-6,670,568 Installation for processing wafers
An installation for processing wafers in at least one clean room is described. The installation has a configuration of production units for carrying out...
US-6,670,244 Method for fabricating a body region for a vertical MOS transistor arrangement having a reduced on resistivity
A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the...
US-6,670,235 Process flow for two-step collar in DRAM preparation
In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing...
US-6,669,857 Process for etching bismuth-containing oxide films
A process is described for etching oxide films containing at least one bismuth-containing oxide, in particular a ferroelectric bismuth-containing mixed oxide. A...
US-6,668,524 Packaging system with a tool for enclosing electronic components, and method of populating a carrying belt
A packaging system and a method of populating a transport belt with a tool for enclosing electronic components in a carrying belt, is described. For this...
US-6,668,356 Method for designing circuits with sections having different supply voltages
In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being...
US-6,668,301 Microcontroller with flexible interface to external device
A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group...
US-6,668,242 Emulator chip package that plugs directly into the target system
The present invention relates to electronic packaging and a method for manufacturing the same. According to an embodiment of the present invention, an emulator...
US-6,668,031 Synchronized data capturing circuits using reduced voltage levels and methods therefor
A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized...
US-6,667,922 Sensing amplifier with single sided writeback
A method of transferring data to a memory storage cell that is attached to a first bitline. The method includes passing a charge representative of data from a...
US-6,667,919 Semiconductor memory device and test method thereof using row compression test mode
A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer...
US-6,667,660 Temperature sensor and circuit configuration for controlling the gain of an amplifier circuit
A temperature sensor has a first FET transistor circuit, whose operating point is located at the temperature-independent point, and a second FET transistor...
US-6,667,633 Multiple finger off chip driver (OCD) with single level translator
A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the...
US-6,667,609 Current generating device with reduced switching time from an energy saving mode
A current generating device is characterized in that it is configured for, in response to a predetermined event, temporarily impresses a current, which is...
US-6,667,514 Semiconductor component with a charge compensation structure and associated fabrication
A semiconductor component includes a charge compensation structure wherein locations with a maximum local field strength are positioned in a compensation edge...
US-6,667,504 Self-aligned buried strap process using doped HDP oxide
The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive...
US-6,667,223 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern
A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active...
US-6,665,846 Method and configuration for verifying a layout of an integrated circuit and application thereof for...
With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in...
US-6,665,802 Power management and control for a microcontroller
A power management system for a microcontroller. The power management system includes a power management state machine for controlling a power mode of a central...
US-6,665,528 Dual band fet mixer
A dual band mixer has a common node for at least one radio frequency input and an intermediate frequency output. The dual band mixer also has a first transistor...
US-6,665,228 Integrated memory having a memory cell array with a plurality of segments and method for operating the...
An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different...
US-6,665,224 Partial refresh for synchronous dynamic random access memory (SDRAM) circuits
A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of...
US-6,665,211 Memory arrangement with selectable memory sectors
In order to achieve a maximally space-saving configuration of a matricial memory arrangement (1), for example in the form of a non-volatile flash memory, which...
US-6,665,197 Circuit configuration for producing a switching signal for a current-controlled switch-mode power supply
A circuit configuration for generating a switching signal for a current controlled switched mode power supply includes a transformer with windings, a controlled...
US-6,665,182 Module unit for memory modules and method for its production
The invention relates to a module unit for memory modules and to a method for producing the module unit. A module unit of this type has at least one main module...
US-6,664,857 Two-stage operational amplifier
A two-stage operational amplifier has an input stage and a downstream output stage. In this configuration, the magnitude of a first supply potential which...
US-6,664,856 Circuit configuration for setting the operating point of a radiofrequency transistor and amplifier circuit
An amplifier circuit with a radiofrequency transistor has a circuit for setting the operating point. The setting circuit provides a base current for the...
US-6,664,648 Apparatus for applying a semiconductor chip to a carrier element with a compensating layer
A method and an apparatus are described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like...
US-6,664,612 Semiconductor component having double passivating layers formed of two passivating layers of different...
A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer...
US-6,664,590 Circuit configuration for load-relieved switching
A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in...
US-6,664,538 Mismatching of gratings to achieve phase shift in an optical position detector
An optical position detector system has a light emitting diode source, two detectors, and a diffraction grating which is frequency mismatched with the frequency...
US-6,664,176 Method of making pad-rerouting for integrated circuit chips
A method for forming printed re-routing for wafer level packaging, especially chip size packaging. The method includes forming a contact layer on a semiconductor...
US-6,664,167 Memory with trench capacitor and selection transistor and method for fabricating it
A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting...
US-6,664,158 Ferroelectric memory configuration and a method for producing the configuration
An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged...
US-6,664,010 OPC method for generating corrected patterns for a phase-shifting mask and its trimming mask and associated...
A method is provided in which a pattern for a phase-shifting mask is firstly corrected in a first correction step. Subsequently, the pattern for the trimming...
US-6,663,674 Method of handling a silicon wafer
A recycling procedure for 300 mm nitride dummy wafers which have a stabilization layer of silicon dioxide is provided. The recycling procedure is essentially...
US-6,662,326 Circuit cell having a built-in self-test function, and test method therefor
The circuit cell for test methods having a built-in self-test function for modular circuits. The cell has a memory unit for storing data, a combinatorial logic...
US-6,662,303 Write precompensation circuit and read channel with write precompensation circuit that generates output signals...
An improved write precompensation circuit. Eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders (104). The phase...
US-6,661,863 Phase mixer
A phase mixer is provided which locks a signal to a non-integer multiple of a reference signal. A phase mixer according to the present invention is provided...
US-6,661,721 Systems and methods for executing precharge commands using posted precharge in integrated circuit memory...
A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM...
US-6,661,718 Testing device for testing a memory
A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory...
US-6,661,701 Three-transistor DRAM cell and associated fabrication method
The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second...
US-6,661,694 Configuration and method for increasing the retention time and the storage security in a ferroelectric or...
A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the...
US-6,661,590 Efficient analog front end for a read/write channel of a hard disk drive running from a highly regulated power...
A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an...
US-6,661,301 Oscillator circuit
An oscillator circuit with connectable capacitance makes it possible for the oscillator to change over between at least two frequencies. A switching unit is...
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