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Self-terminating blow process of electrical anti-fuses
An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18)....
Miniaturized capacitor with solid-state dielectric, in particular for
integrated semiconductor memories, E.G....
A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface...
The holder is suitable for detachably fixing a component in an operational end position. The holder has an upper side on which the component is moved into the...
Circuit configuration for the interference-free initialization of delay
locked loop circuits with fast lock
The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for...
Method and apparatus for producing spread-coded signals
Transmission data that will be transmitted is coded and thus band-spread using a spread code. The band-spread transmission data is also coded using a scrambling...
Semiconductor memory with refresh and method for operating the
To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal...
Integrated memory and method for testing an integrated memory
An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to...
Memory chip having a test mode and method for checking memory cells of a
repaired memory chip
The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a...
Method and circuit configuration for a memory for reducing parasitic
A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two...
Configuration and method for the low-loss writing of an MRAM
A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells...
The data memory device has a plurality of memory cells for storing data which are represented by a first physical value of the storing memory elements,...
An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage...
Current mirror and method for operating a current mirror
A current mirror and method for operating such a mirror include nonlinearly converting an input current (I.sub.in.sup.+ =I.sub.0 and, respectively, ...
Adjustable frequency divider
The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the...
Free wheeling buck regulator with floating body zone switch
A voltage transformer includes a pair of input terminals for applying an input voltage, a series circuit connected in parallel to the pair of input terminals of...
Charge compensation semiconductor configuration
Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric...
Electrically programmable memory cell configuration and method for
A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the...
Integrated circuit and method for fabricating an integrated circuit
An integrated circuit includes a first circuit section and a second circuit section, which is necessary or useful for the emulation of the first circuit section....
Forming a structure on a wafer
A method for fabricating a structure on an integrated circuit (IC) wafer, includes providing a material onto a surface of the wafer and shaping the material to...
Dual hardmask single damascene integration scheme in an organic low k ILD
Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD)...
Method for producing an insulation
A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an...
Method for producing a memory cell for a semiconductor memory
The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole,...
Method of making resistive memory elements with reduced roughness
A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed...
Optical coupling configuration
The optic coupling system links a fiber-optics waveguide with two optoelectronic components. The components are disposed on a substrate with an interposed...
Phase locked loop system
A phase locked loop system for tuning the reception frequency of a receiver for digitally modulated received signals and analog-modulated received signals has at...
Memory circuit having a plurality of memory areas
A memory circuit has at least two memory areas each including a group of primary read amplifiers. Each of these groups can be connected via an assigned local...
Memory module, method for activating a memory cell, and method for
repairing a defective memory cell
In the memory module, depending on the configuration chosen, the number of redundant memory cells which is assigned to a defective address is also adapted to the...
Accumulating read channel performance data
Systems and methods for accumulating data relating to the performance of one or more components of a read channel are described. In one aspect, a programmable...
Method and input circuit for evaluating a data signal at an input of a
The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is...
Sensor apparatus and method for generating an output signal of a sensor
A sensor apparatus having a sensor for generating an analog sensor signal with successive minima and maxima is provided. The apparatus can include a first output...
Monolithically integrable inductor
A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one...
Power semiconductor component having a PN junction with a low area edge
Component having a blocking pn junction having an edge termination structure which is formed by a further, more weakly doped region (5) and a trench (8) formed...
A protective circuit for limiting a voltage at a pad of an integrated circuit includes a threshold selector connected between the pad and ground. The input...
Method of producing alignment marks
Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are...
Semiconductor structure and method of fabrication including forming
High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the...
Method and manufacturing MRAM offset cells in a damascene structure
A method of manufacturing an offset MRAM device (110), including utilizing two resist layers either to pattern a magnetic stack layer to form offset conductive...
Method for fabricating a bipolar transistor and method for fabricating an
integrated circuit configuration...
The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar...
Structure and method for dual work function logic devices in vertical DRAM
Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56...
Plate-through hard mask for MRAM devices
A method of fabricating an MRAM device includes patterning a magnetic stack material layer (142) using a herd mask (146) formed by a "plate-through" technique. A...
Metallizing method for dielectrics
A method for metallizing dielectrics includes applying a photosensitive dielectric to a substrate. The dielectric is then exposed to light through a mask, is...
Contact hole fabrication with the aid of mutually crossing sudden phase
shift edges of a single phase shift mask
The invention relates to a phase shift mask for lithographically producing small structures at the limit of a resolution that is predetermined by the wavelength...
Optoelectronic module for bidirectional optical data transmission
An optoelectric module for bidirectional optical data transmission has a molded element provided as a beam splitter, which consists essentially of a material...
Integrated circuit and circuit configuration for supplying power to an
An integrated circuit for processing security-relevant data has data output circuits and access control circuits wherein a disturbance of the power supply of the...
Method and apparatus for compensation of second order distortion
A method and apparatus for removing second order distortion is disclosed. The method couples a differential load between two source followers of a gain stage....
Apparatus and method for measuring the degradation of a tool
A machining apparatus (10) comprises a material removing tool (12) movably mounted for removing material from a workpiece (14); means for illuminating (42, 54) a...
Compensation component with improved robustness
The compensation component is formed with compensation regions in a semiconductor between two electrodes. By varying the second field and/or the first field, a...
SOI substrate, a semiconductor circuit formed in a SOI substrate, and an
associated production method
In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier...
Methods of compensating for wafer parameters
The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is...
Generating mask layout data for simulation of lithographic processes
A method for generating mask layout data for lithography simulation includes prescribing original data defining an original layout of a mask and determining a...
Modularly expandable multi-layered semiconductor component
A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one...