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Patent # Description
US-6,642,602 Self-terminating blow process of electrical anti-fuses
An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18)....
US-6,642,565 Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G....
A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface...
US-6,641,416 Mounting holder
The holder is suitable for detachably fixing a component in an operational end position. The holder has an upper side on which the component is moved into the...
US-6,639,958 Circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock
The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for...
US-6,639,937 Method and apparatus for producing spread-coded signals
Transmission data that will be transmitted is coded and thus band-spread using a spread code. The band-spread transmission data is also coded using a scrambling...
US-6,639,862 Semiconductor memory with refresh and method for operating the semiconductor memory
To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal...
US-6,639,861 Integrated memory and method for testing an integrated memory
An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to...
US-6,639,856 Memory chip having a test mode and method for checking memory cells of a repaired memory chip
The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a...
US-6,639,846 Method and circuit configuration for a memory for reducing parasitic coupling capacitances
A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two...
US-6,639,829 Configuration and method for the low-loss writing of an MRAM
A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells...
US-6,639,825 Data memory
The data memory device has a plurality of memory cells for storing data which are represented by a first physical value of the storing memory elements,...
US-6,639,824 Memory architecture
An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage...
US-6,639,456 Current mirror and method for operating a current mirror
A current mirror and method for operating such a mirror include nonlinearly converting an input current (I.sub.in.sup.+ =I.sub.0 and, respectively, ...
US-6,639,435 Adjustable frequency divider
The novel frequency divider has an adjustable divider ratio. Such circuits are subject to demands for ever higher clock frequencies. The circuit generates the...
US-6,639,388 Free wheeling buck regulator with floating body zone switch
A voltage transformer includes a pair of input terminals for applying an input voltage, a series circuit connected in parallel to the pair of input terminals of...
US-6,639,272 Charge compensation semiconductor configuration
Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric...
US-6,639,269 Electrically programmable memory cell configuration and method for fabricating it
A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the...
US-6,639,252 Integrated circuit and method for fabricating an integrated circuit
An integrated circuit includes a first circuit section and a second circuit section, which is necessary or useful for the emulation of the first circuit section....
US-6,638,870 Forming a structure on a wafer
A method for fabricating a structure on an integrated circuit (IC) wafer, includes providing a material onto a surface of the wafer and shaping the material to...
US-6,638,851 Dual hardmask single damascene integration scheme in an organic low k ILD
Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD)...
US-6,638,814 Method for producing an insulation
A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an...
US-6,638,812 Method for producing a memory cell for a semiconductor memory
The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole,...
US-6,638,774 Method of making resistive memory elements with reduced roughness
A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed...
US-6,637,947 Optical coupling configuration
The optic coupling system links a fiber-optics waveguide with two optoelectronic components. The components are disposed on a substrate with an interposed...
US-6,636,727 Phase locked loop system
A phase locked loop system for tuning the reception frequency of a receiver for digitally modulated received signals and analog-modulated received signals has at...
US-6,636,453 Memory circuit having a plurality of memory areas
A memory circuit has at least two memory areas each including a group of primary read amplifiers. Each of these groups can be connected via an assigned local...
US-6,636,447 Memory module, method for activating a memory cell, and method for repairing a defective memory cell
In the memory module, depending on the configuration chosen, the number of redundant memory cells which is assigned to a defective address is also adapted to the...
US-6,636,372 Accumulating read channel performance data
Systems and methods for accumulating data relating to the performance of one or more components of a read channel are described. In one aspect, a programmable...
US-6,636,097 Method and input circuit for evaluating a data signal at an input of a memory component
The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is...
US-6,636,033 Sensor apparatus and method for generating an output signal of a sensor apparatus
A sensor apparatus having a sensor for generating an analog sensor signal with successive minima and maxima is provided. The apparatus can include a first output...
US-6,635,947 Monolithically integrable inductor
A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one...
US-6,635,944 Power semiconductor component having a PN junction with a low area edge termination
Component having a blocking pn junction having an edge termination structure which is formed by a further, more weakly doped region (5) and a trench (8) formed...
US-6,635,930 Protective circuit
A protective circuit for limiting a voltage at a pad of an integrated circuit includes a threshold selector connected between the pad and ground. The input...
US-6,635,567 Method of producing alignment marks
Alignment marks (overlay marks or alignment markers) are produced in a semiconductor structure with integrated circuits. Contact holes and alignment trenches are...
US-6,635,564 Semiconductor structure and method of fabrication including forming aluminum columns
High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the...
US-6,635,546 Method and manufacturing MRAM offset cells in a damascene structure
A method of manufacturing an offset MRAM device (110), including utilizing two resist layers either to pattern a magnetic stack layer to form offset conductive...
US-6,635,545 Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration...
The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar...
US-6,635,526 Structure and method for dual work function logic devices in vertical DRAM process
Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56...
US-6,635,496 Plate-through hard mask for MRAM devices
A method of fabricating an MRAM device includes patterning a magnetic stack material layer (142) using a herd mask (146) formed by a "plate-through" technique. A...
US-6,635,410 Metallizing method for dielectrics
A method for metallizing dielectrics includes applying a photosensitive dielectric to a substrate. The dielectric is then exposed to light through a mask, is...
US-6,635,388 Contact hole fabrication with the aid of mutually crossing sudden phase shift edges of a single phase shift mask
The invention relates to a phase shift mask for lithographically producing small structures at the limit of a resolution that is predetermined by the wavelength...
US-RE38,280 Optoelectronic module for bidirectional optical data transmission
An optoelectric module for bidirectional optical data transmission has a molded element provided as a beam splitter, which consists essentially of a material...
US-6,633,501 Integrated circuit and circuit configuration for supplying power to an integrated circuit
An integrated circuit for processing security-relevant data has data output circuits and access control circuits wherein a disturbance of the power supply of the...
US-6,633,447 Method and apparatus for compensation of second order distortion
A method and apparatus for removing second order distortion is disclosed. The method couples a differential load between two source followers of a gain stage....
US-6,633,379 Apparatus and method for measuring the degradation of a tool
A machining apparatus (10) comprises a material removing tool (12) movably mounted for removing material from a workpiece (14); means for illuminating (42, 54) a...
US-6,633,064 Compensation component with improved robustness
The compensation component is formed with compensation regions in a semiconductor between two electrodes. By varying the second field and/or the first field, a...
US-6,633,061 SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method
In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier...
US-6,632,687 Methods of compensating for wafer parameters
The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is...
US-6,631,511 Generating mask layout data for simulation of lithographic processes
A method for generating mask layout data for lithography simulation includes prescribing original data defining an original layout of a mask and determining a...
US-6,630,727 Modularly expandable multi-layered semiconductor component
A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one...
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