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Patent # Description
US-6,680,151 Alternating phase mask
An alternating phase mask is described in which a propagation of a T phase conflict which occurs in the case of a T pattern structure is avoided by producing a...
US-6,677,813 Integrated circuit for receiving a clock signal, particularly for a semiconductor memory circuit
An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A...
US-6,677,806 Charge pump for generating high voltages for semiconductor circuits
The charge pump generates high voltages for integrated semiconductor circuits. The charge pump has a plurality of pump stages with at least one power transistor...
US-6,677,770 Programmable test socket
A test socket for a semiconductor device includes a guide plate operable to receive the semiconductor device and to maintain electrical terminals of the...
US-6,677,745 Test apparatus for parallel testing a number of electronic components and a method for calibrating the test...
A method for calibrating a test apparatus for parallel testing of a number of semiconductor memories, to a time-critical parameter, in which the components are...
US-6,677,635 Stacked MIMCap between Cu dual damascene levels
A semiconductor device includes a structure composed of a first inter-level-dielectric with an embedded first Cu dual damascene level. A dielectric is coated on...
US-6,677,630 Semiconductor device having ferroelectric film and manufacturing method thereof
First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor...
US-6,677,218 Method for filling trenches in integrated semiconductor circuits
A method in which a recess is formed in the surface of a semiconductor substrate and a material is grown on the inner wall of the recess, includes the steps of...
US-6,677,205 Integrated spacer for gate/source/drain isolation in a vertical array structure
Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two...
US-6,677,197 High aspect ratio PBL SiN barrier formation
In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of...
US-6,674,813 Integrated circuit for detecting a received signal and circuit configuration
In order to detect a received signal quickly and reliably, an integrated circuit for detecting a received signal has an intermediate frequency detector which...
US-6,674,774 Chopped laser driver for low noise applications
A circuit (10) for driving a laser diode (12) includes a fixed current source (14), a programmable current source (16), a differential output driver (18), a...
US-6,674,684 Multi-bank chip compatible with a controller designed for a lesser number of banks and method of operating
A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a...
US-6,674,674 Method for recognizing and replacing defective memory cells in a memory
A method for recognizing a defective memory cell in a memory having a plurality of memory cells includes directly comparing predetermined properties of the...
US-6,674,627 Needle-card adjusting device for planarizing needle sets on a needle card
A needle-card adjusting device for planarizing needle sets on a needle card, in which the needle card is connected to a circuit board used as a contact interface...
US-6,674,322 Amplifier circuit with offset compensation
An amplifier circuit with offset compensation is particularly suited for a Hall element. In addition to the useful signal demodulation that is normally present...
US-6,674,132 Memory cell and production method
A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region...
US-6,674,113 Trench capacitor and method for manufacturing the same
A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first...
US-6,673,693 Method for forming a trench in a semiconductor substrate
A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is...
US-6,673,686 Method of forming a gate electrode contact spacer for a vertical DRAM device
A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches...
US-6,673,677 Method for manufacturing a multi-bit memory cell
A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge...
US-6,673,189 Method for producing a stable bond between two wafers
A method for producing a re-releasable bond between two wafers which is stable at high temperatures and mechanically stable is described. The two wafers to be...
US-6,672,901 Housing for plug-connected electrical component and method of mounting such a housing on a printed circuit board
A connector for a plug-connected electrical component, in particular, an optoelectronic transceiver, includes a package having fastening pins for fastening the...
US-6,671,439 Integrated waveguide arrangement, process for producing an integrated waveguide arrangement, and waveguide...
The invention explains, inter alia, integrated waveguide arrangements in which a waveguide with glass core and glass sheath is arranged in a waveguide layer...
US-6,671,221 Semiconductor chip with trimmable oscillator
A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the...
US-6,670,827 Tri-state driver arrangement
A tri-state driver arrangement has a coupler (2) for the potential-free transmission of signals between an input and an output of the tri-state driver...
US-6,670,802 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits
Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven...
US-6,670,668 Microelectronic structure, method for fabricating it and its use in a memory cell
A microelectronic structure that is suitable, in particular, as part of a storage capacitor includes a semiconductor structure, a barrier structure, an electrode...
US-6,670,665 Memory module with improved electrical properties
A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of...
US-6,670,662 Semiconductor storage component with storage cells, logic areas and filling structures
The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions...
US-6,670,661 Ferroelectric memory cell with diode structure to protect the ferroelectric during read operations
A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between...
US-6,670,646 Mask and method for patterning a semiconductor wafer
A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122)....
US-6,670,568 Installation for processing wafers
An installation for processing wafers in at least one clean room is described. The installation has a configuration of production units for carrying out...
US-6,670,244 Method for fabricating a body region for a vertical MOS transistor arrangement having a reduced on resistivity
A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the...
US-6,670,235 Process flow for two-step collar in DRAM preparation
In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing...
US-6,669,857 Process for etching bismuth-containing oxide films
A process is described for etching oxide films containing at least one bismuth-containing oxide, in particular a ferroelectric bismuth-containing mixed oxide. A...
US-6,668,524 Packaging system with a tool for enclosing electronic components, and method of populating a carrying belt
A packaging system and a method of populating a transport belt with a tool for enclosing electronic components in a carrying belt, is described. For this...
US-6,668,356 Method for designing circuits with sections having different supply voltages
In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being...
US-6,668,301 Microcontroller with flexible interface to external device
A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group...
US-6,668,242 Emulator chip package that plugs directly into the target system
The present invention relates to electronic packaging and a method for manufacturing the same. According to an embodiment of the present invention, an emulator...
US-6,668,031 Synchronized data capturing circuits using reduced voltage levels and methods therefor
A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized...
US-6,667,922 Sensing amplifier with single sided writeback
A method of transferring data to a memory storage cell that is attached to a first bitline. The method includes passing a charge representative of data from a...
US-6,667,919 Semiconductor memory device and test method thereof using row compression test mode
A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer...
US-6,667,660 Temperature sensor and circuit configuration for controlling the gain of an amplifier circuit
A temperature sensor has a first FET transistor circuit, whose operating point is located at the temperature-independent point, and a second FET transistor...
US-6,667,633 Multiple finger off chip driver (OCD) with single level translator
A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the...
US-6,667,609 Current generating device with reduced switching time from an energy saving mode
A current generating device is characterized in that it is configured for, in response to a predetermined event, temporarily impresses a current, which is...
US-6,667,514 Semiconductor component with a charge compensation structure and associated fabrication
A semiconductor component includes a charge compensation structure wherein locations with a maximum local field strength are positioned in a compensation edge...
US-6,667,504 Self-aligned buried strap process using doped HDP oxide
The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive...
US-6,667,223 High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern
A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active...
US-6,665,846 Method and configuration for verifying a layout of an integrated circuit and application thereof for...
With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in...
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