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Patent # Description
US-6,696,872 Delay locked loop compensating for effective loads of off-chip drivers and methods for locking a delay loop
A delay locked loop (DLL) for use in a semiconductor device includes a phase detector that receives a reference clock signal and a feedback clock signal and...
US-6,696,759 Semiconductor device with diamond-like carbon layer as a polish-stop layer
A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a...
US-6,696,742 Semiconductor memory device
A semiconductor memory device includes a semiconductor substrate having a first conductivity type and multiple parallel trenches extending in a first direction...
US-6,696,371 Method for fabricating positionally exact surface-wide membrane masks
The membrane mask is based on an SOI substrate. In an existing or subsequently produced multilayer semiconductor/insulator/semiconductor-carrier-layer substrate,...
US-6,696,349 STI leakage reduction
A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to...
US-6,696,335 Method for forming a diffusion region
For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal ...
US-6,696,319 Method of attaching semiconductor devices on a switching device and such an attached device
A method of attaching semiconductor devices, the contact devices of which have preferably already been applied at wafer level, on a switching device and such a...
US-6,696,315 Semiconductor device configuration with cavities of submicrometer dimensions and method of fabricating...
Cavities of submicron dimension are in a cavity layer of a semiconductor device. For that purpose, processing material is deposited on ridges of a working layer...
US-6,696,208 Method for experimentally verifying imaging errors in optical exposure units
Imaging errors in optical exposure units for the lithographic structuring of semiconductors are determined. First, a latent image of a mask is first produced in...
US-6,696,206 Lithography mask configuration
A reflective membrane mask is composed at least partially of an electrically conductive material and is aligned horizontally over a sample to be processed....
US-6,695,687 Semiconductor substrate holder for chemical-mechanical polishing containing a movable plate
A substrate holder is described which has a movable plate elastically mounted inside a main body. With the substrate holder, a polishing operation can be...
US-6,694,707 Apparatus and method for populating transport tapes
An apparatus and a method for populating transport tapes with electronic components includes a mold support having at least one recess over which a flat plastic...
US-6,694,423 Prefetch streaming buffer
A data processing unit having superscalar structure able to execute a plurality of instructions in parallel includes a memory for storing the instructions having...
US-6,694,282 Method and device for determining an operating temperature of a semiconductor component
A method and a device determine an operating temperature of a semiconductor component during operation, wherein the semiconductor component has a PROM memory...
US-6,694,102 Optical configuration, in particular for bidirectional WDM systems, and a transceiving module for bidirectional...
An optical configuration includes a Mach-Zehnder interferometer and a directional coupler. Both the Mach-Zehnder interferometer and the directional coupler have...
US-6,694,074 Transmission and reception configuration for bi-directional optical data transmission
A transmission and reception configuration for bi-directional optical data transmission, in particular, through plastic-fiber optical waveguides, includes a...
US-6,693,846 Command controller for an integrated circuit memory device and test circuitry thereof
A circuit configuration contains a flow controller that can be put into a plurality of states and outputs a respective command, in a respective one of the...
US-6,693,843 Wordline on and off voltage compensation circuit based on the array device threshold voltage
An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage ("V.sub.T...
US-6,693,483 Charge pump configuration having closed-loop control
A charge pump configuration for matching a charge pump to prevailing conditions is described. The charge pump configuration according to the invention has a...
US-6,693,473 Delay lock loop having a variable voltage regulator
A delay lock loop circuit includes a forward delay circuit having a plurality of delay elements. Each delay element has a delay time of one unit delay time. The...
US-6,693,416 Method and device for measuring the phase shift between a periodic signal and an output signal at an output of...
A method and a device for measuring a phase shift between a periodic signal and an output signal at an output of an electronic component. A supply voltage...
US-6,693,343 Self-passivating Cu laser fuse
In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and...
US-6,693,318 Reduced diffusion of a mobile specie from a metal oxide ceramic
A barrier layer is provided to prevent the diffusion of excess mobile specie from a metal oxide ceramic into the substrate. The barrier layer is provided below...
US-6,693,312 Method for fabricating an optical transmitting subassembly
A photo-optical transmitter assembly is produced in the following manner: a glass wafer is fixed onto a transparent submount and a V-shaped recess is ...
US-6,693,024 Semiconductor component with a semiconductor body having a multiplicity of pores and method for fabricating
The semiconductor component is fabricated on the basis of a semiconductor body with a first and a second surface. A multiplicity of pores are formed in the...
US-6,693,022 CVD method of producing in situ-doped polysilicon layers and polysilicon layered structures
Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by...
US-6,693,017 MIMcap top plate pull-back
A MIM capacitor includes a bottom plate, a capacitor dielectric disposed over the bottom plate, and a top plate disposed over the capacitor dielectric. An etch...
US-6,693,016 Method of fabricating a trench-structure capacitor device
The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include...
US-6,692,898 Self-aligned conductive line for cross-point magnetic memory integrated circuits
Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A...
US-6,692,875 Mask for optical projection systems, and a process for its production
A mask contains a transparent carrier material on which an opaque region is disposed as an image structure. Also disposed on the carrier material is a ...
US-6,690,985 Method for the hybrid-automated monitoring of production machines
The method is for generating production information, such as capacity, reliability, or capacity utilization information, while hybrid-automated monitoring a...
US-6,690,612 Voltage supply for semiconductor memory
The invention relates to a voltage supply arrangement for a semiconductor memory with a bus system that is terminated on one side. A terminating voltage supply...
US-6,690,605 Logic signal level converter circuit and memory data output buffer using the same
A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level...
US-6,690,556 Integrated circuit
An integrated circuit with at least one antenna for the contactless transmission of data or energy. The antenna is configured above and/or below circuit sections...
US-6,690,525 High-speed programmable synchronous counter for use in a phase locked loop
A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant...
US-6,690,210 Transmitting device
A transmitting device generates a modulation signal depending on data to be transmitted. The transmitting device includes a transmission frequency generation...
US-6,690,209 Phase detecting with parallel discharge paths
Improved systems and methods of phase detecting are described. In one aspect, a phase detector includes a latch having an input stage and an output stage. The...
US-6,690,198 Repeater with reduced power consumption
A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from...
US-6,690,062 Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain...
The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least...
US-6,689,691 Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a...
The method allows simultaneous polishing of a plurality of objects of a similar type, preferably silicon wafers. The polishing process is interrupted briefly at...
US-6,687,726 Apparatus for multiplication by constant factors for video compression method (MPEG)
Particularly with relatively complex multiplication devices with a downstream shift device, such as those which occur in video compression devices, the apparatus...
US-6,687,171 Flexible redundancy for memories
An improved redundancy scheme for a memory matrix is disclosed. The memory matrix a plurality of memory cells interconnected in first and second directions. The...
US-6,687,170 System and method for storing parity information in fuses
A system and method for determining the accuracy of the states of fuses by changing, or not changing, the state of additional fuses. The system includes a memory...
US-6,687,163 Semiconductor memory arrangement
To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a...
US-6,687,150 Reference voltage generation for memory circuits
An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and...
US-6,687,014 Method for monitoring the rate of etching of a semiconductor
A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate...
US-6,686,805 Ultra low jitter clock generation device and method for storage drive and radio frequency systems
A clock generation device includes a delay-locked loop and a plurality of programmable counters. The plurality of programmable counters are coupled to...
US-6,686,798 Reference voltage circuit
Reference voltage circuit for generating at least one constant reference voltage (V.sub.ref) with a first current mirror circuit (54), which is connected to a...
US-6,686,764 Apparatus and method for reducing reflexions in a memory bus system
The present invention relates to an apparatus and a method for reducing reflexions in a bus for transmitting data. The device comprises an output, which is...
US-6,686,668 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask
A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed....
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