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Mismatching of gratings to achieve phase shift in an optical position
An optical position detector system has a light emitting diode source, two detectors, and a diffraction grating which is frequency mismatched with the frequency...
Method of making pad-rerouting for integrated circuit chips
A method for forming printed re-routing for wafer level packaging, especially chip size packaging. The method includes forming a contact layer on a semiconductor...
Memory with trench capacitor and selection transistor and method for
A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting...
Ferroelectric memory configuration and a method for producing the
An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged...
OPC method for generating corrected patterns for a phase-shifting mask and
its trimming mask and associated...
A method is provided in which a pattern for a phase-shifting mask is firstly corrected in a first correction step. Subsequently, the pattern for the trimming...
Method of handling a silicon wafer
A recycling procedure for 300 mm nitride dummy wafers which have a stabilization layer of silicon dioxide is provided. The recycling procedure is essentially...
Circuit cell having a built-in self-test function, and test method therefor
The circuit cell for test methods having a built-in self-test function for modular circuits. The cell has a memory unit for storing data, a combinatorial logic...
Write precompensation circuit and read channel with write precompensation
circuit that generates output signals...
An improved write precompensation circuit. Eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders (104). The phase...
A phase mixer is provided which locks a signal to a non-integer multiple of a reference signal. A phase mixer according to the present invention is provided...
Systems and methods for executing precharge commands using posted precharge
in integrated circuit memory...
A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM...
Testing device for testing a memory
A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory...
Three-transistor DRAM cell and associated fabrication method
The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second...
Configuration and method for increasing the retention time and the storage
security in a ferroelectric or...
A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the...
Efficient analog front end for a read/write channel of a hard disk drive
running from a highly regulated power...
A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an...
An oscillator circuit with connectable capacitance makes it possible for the oscillator to change over between at least two frequencies. A switching unit is...
Circuit arrangement and method for discharging at least one circuit node
In a circuit arrangement for discharging at least one circuit node, an input and at least one output connectible to the at least one circuit node are provided...
Delay locked loop for generating complementary clock signals
A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary...
Circuit configuration with a load transistor and a current measuring
A circuit configuration includes a load transistor having a control terminal, a first load path terminal connected to a first supply potential, and a second load...
Controlling a brushless DC motor
Systems and methods for controlling a polyphase brushless direct current (DC) motor (42) are described. One system includes a meter (14) coupled to a motor...
Three-dimensionally embodied circuit with electrically connected
The invention relates to a three-dimensional circuit configuration in which semiconductor chips are configured one above the other and in which the semiconductor...
Memory cell with trench transistor
A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body...
Shielding element for electromagnetic shielding of an aperture opening
The invention relates to a shielding element for electromagnetically shielding an aperture opening formed, for example, in a metallic structure, a plug holder or...
Fabrication method and apparatus for fabricating a spatial structure in a
In a fabrication method for making spatially etched structures, in particular trench structures for semiconductor memory cells, in a semiconductor substrate made...
Process for chemical mechanical polishing
A chemical mechanical polishing process rotates a wafer having an alignment mark at a wafer rotation rate and a polishing surface at an off-matched rotation...
Method of forming a vertical field-effect transistor device
It is proposed when forming field-effect transistor devices in a semiconductor substrate for the overlapping region of a source-drain region that is to be...
Alternating phase mask
An alternating phase mask having a branched structure containing two opaque segments is described. Two transparent surface segments are disposed on both sides of...
Method and apparatus for monitoring a process that proceeds automatically
to ensure that it is executed properly
A method and an apparatus for monitoring a process that proceeds automatically to ensure that it is executed properly. The method and the apparatus are...
Method and circuit for compensation control of offset voltages in a radio
receiving circuit integrated in a...
Offset voltage compensation in baseband in a radio receiver path is achieved by control and programming signals which are required in any case to set the desired...
Codec circuit and method for increasing the data transmission rate during a
Codec circuit for increasing the data transmission rate in a modem transmission with a first programmable digital filter (13) which is connected into a...
Integrated memory with memory cell array
An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one...
Memory sense amplifier
Memory sense amplifier unit for amplifying a data signal read from a memory via bit lines (2, 3), having a precharge circuit (4) comprising PMOS transistors (5,...
Phase assisted synchronization detector
A synchronization detector including a phase detector and a distance metric calculator. The phase detector uses the preamble readback signal to estimate the bit...
Configuration having a current source and a switch connected in series
The configuration described is distinguished by the fact that it contains a control device which ensures that the potential which is established on the...
Semiconductor wafer testing system and method
An apparatus for testing a plurality of semiconductor devices of a common wafer includes a plurality of driver circuits, each operable to produce an intermediate...
Configuration for measurement of internal voltages of an integrated
The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and...
Current mirror circuit
A current mirror circuit has an input path, which has a current source and, connected in series therewith, a first transistor circuit with at least two...
Thin film piezoelectric resonator
The layer of the cover electrode, or an additional layer on the cover electrode is formed with holes, preferably produced lithographically, or similar...
Manipulation-proof integrated circuit
The integrated circuit has a circuit with information that is protected by a covering shielding level. A network with a large number of nodes is formed in the...
Gate processing method with reduced gate oxide corner and edge thinning
Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an...
Method for fabricating non-volatile memories
A method for fabricating a semiconductor component includes the steps of applying an electrode material and a metal-oxide-containing layer on a substrate surface...
Method for examining structures on a wafer
In a method for examining structures on a wafer, at least one mask, which is applied on the wafer and is fabricated by exposure processes, is used for...
Method for authorization checking and configuration for carrying out the
The system checks whether authorization exists for at least two data processing devices to exchange data with one another. In the preferred embodiment, both data...
Nonvolatile nor semiconductor memory device and method for programming the
A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of ...
Method for reading and storing binary memory cells signals and circuit
The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one...
Method and apparatus for the A/D conversion of analog signals and
corresponding A/D converter arrangement
An A/D converter arrangement comprises an A/D converter (6) to which analog signals from a plurality of signal channels (2) can be fed for A/D conversion. With...
Output drivers for IC
The invention features an output driver for integrated circuits that includes a driver that has a data input connected to the integrated circuit, a data output...
Method and system for managing a pulse width of a signal pulse
An input signal is received having a period and an input pulse width. The input pulse width of an input signal is adjusted to an output pulse width of an output...
Method and apparatus for a delay lock loop
A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit...
Electronic component having a semiconductor chip
An electronic component includes a semiconductor chip and/or a test structure. The semiconductor chip includes a multi-layer coating having at least one...
Method of providing trench walls by using two-step etching processes
Method of providing trench walls of a uniform orientation to support epitaxial growth in the trench. The trench is formed by a first etching process. A second...