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Patent # Description
US-6,844,603 Nonvolatile NOR two-transistor semiconductor memory cell and associated NOR semiconductor memory device and...
The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication...
US-6,844,584 Memory cell, memory cell configuration and fabrication method
Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located...
US-6,844,581 Storage capacitor and associated contact-making structure and a method for fabricating the storage capacitor...
A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that...
US-6,844,245 Method of preparing a self-passivating Cu laser fuse
A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a...
US-6,842,887 Data processing system for designing a layout of an integrated electronic circuit having a multiplicity of...
A data processing system includes a data memory, in which data are stored, the data representing a set of predetermined geometrical basic forms and a set of...
US-6,842,882 Method for determining, on a basis of a circuit diagram of a digital circuit, a current drawn by the digital...
The current that will be drawn by a digital circuit is predicted on the basis of its schematic circuit diagram. An equivalent circuit is generated, wherein...
US-6,842,712 Method for testing an electronic component; computer program product, computer readable medium, and computer...
A method tests an electronic component, especially a memory chip, which is connected to a computer system. Initially, test patterns and AC-/DC-parameters are...
US-6,842,542 Method and device for capacitive image acquisition
The sensor is provided for the capacitive acquisition of images, in particular fingerprint images. The capacitors assigned to each pixel are supplemented by...
US-6,842,517 Meter pulse filtering circuit for analog modems
A filtering circuit is described for filtering out meter pulses of analog telephone communication, for example in analog modems. The circuit is mainly composed...
US-6,842,363 Magnetoresistive memory and method for reading a magnetoresistive memory
A magnetoresistive memory includes a control circuit with a first pole that, via a reading distributor, can be individually connected to first ends of bit lines...
US-6,842,260 Imaging system and method for positioning a measuring tip onto a contact region of a microchip
The imaging system provides assistance during the positioning of a measuring tip as it is placed onto a contact region of a microchip, in order to measure an...
US-6,842,235 Optical measurement of planarized features
There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A...
US-6,842,222 Method of reducing pitch on semiconductor wafer
A projected image is formed during a material substrate. A photolithographic mask is illuminated with substantially coherent light at an oblique angle of...
US-6,842,094 Electronic component containing capacitance diodes, having different capacitance ranges, and circuit...
An electronic component has at least a first diode and a second diode that are capacitance diodes. The characteristic curve of the second diode has a fixed,...
US-6,842,083 Component having an integrated radiofrequency circuit
A conductor network includes trimming capacitors and is connected in parallel with a resonant circuit. The trimming capacitors can be connected in parallel with...
US-6,841,978 Voltage regulator with frequency response correction
A voltage regulator has a voltage regulator output (6) for providing a regulated output voltage (Uout) and an internal nonreactive resistor (RZ) arranged in...
US-6,841,973 DC-DC conversion charging apparatus
The present invention provides a method of charging a rechargeable device (108) and a charging apparatus wherein the rechargeable device (108) is connected to a...
US-6,841,922 Piezoelectric resonator apparatus with acoustic reflector
A resonator apparatus has a piezoelectric resonator as well as an acoustic reflector which has a layer having a high acoustic impedance and a layer having a low...
US-6,841,857 Electronic component having a semiconductor chip, system carrier, and methods for producing the electronic...
An electronic component and a system carrier having a heat conduction block, on which overlapping inner flat conductor ends are fixed mechanically and insulated...
US-6,841,824 Flash memory cell and the method of making separate sidewall oxidation
A process and product for making integrated circuits with dense logic and/or linear regions and dense memory regions is disclosed. On a common substrate, a dual...
US-6,841,786 Method and configuration for compensating for unevenness in the surface of a substrate
In a EUV reflection mask, the distance from the surface of the mask to an idealized plane is locally measured at a first position. The measured value indicates...
US-6,841,481 Etching process for a two-layer metallization
The novel etching process for a two-layer metallization, or dual damascene patterning, is simple and cost-effective to carry out and reliably prevents fences...
US-6,841,480 Polyelectrolyte dispensing polishing pad, production thereof and method of polishing a substrate
A polyelectrolyte dispensing polishing pad, a process for its production and a method of polishing, e.g., chemical mechanical polishing (CMP), a substrate such...
US-6,841,448 Method for fabricating embedded nonvolatile semiconductor memory cells
A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having...
US-6,841,443 Method for fabricating a deep trench capacitor for dynamic memory cells
A method for fabricating a deep trench capacitor for dynamic memory cells in which a trench is etched into the depth of a semiconductor substrate, and wherein...
US-6,841,332 Photoresist compound and method for structuring a photoresist layer
A photoresist compound or composition achieves a uniform volume growth in a chemical expansion on a chemically expandable photomask during a method for...
US-6,841,316 Method for producing a phase shift mask
To avoid charging effects of isolated chromium structures during the structuring of a second level of attenuated phase shift masks, a previous chromium etching...
US-6,840,808 Connector for a plurality of switching assemblies with compatible interfaces
A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching...
US-6,840,778 Contact base with detachable contacts for making electrical contact with an electronic component, in particular...
A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic...
US-6,840,684 Housing for a coupling configuration for injecting and/or extracting optical signals
A housing for a coupling configuration for injecting or extracting optical signals of at least one optical data channel into or from an optical conductor has a...
US-6,839,962 Method of producing micromechanical structures
A micromechanical structure is described which is disposed on a base body and requires protection from environmental influences by a covering body. Furthermore,...
US-6,839,397 Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits
A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage...
US-6,839,298 Zero static power fuse cell for integrated circuits
A fuse cell with reduced or no static power dissipation is disclosed. The fuse cell utilizes a latch to store the state of the fuse. The use of the latch avoids...
US-6,839,288 Latch scheme with invalid command detector
Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced...
US-6,839,287 Method of storing a quantity of data in a target memory location and storage system
In a method of storing a quantity of data in a target memory location, the data quantity is stored first in a non-volatile buffer memory location. It is then...
US-6,839,267 Structure and method of multiplexing bitline signals within a memory array
An integrated circuit memory is provided in which a multiplexer is operable to select one of a plurality of bitlines to couple to a master bitline using select...
US-6,839,241 Circuit module
A circuit module comprises a circuit board having a plurality of contact elements along a longitudinal edge thereof. The circuit board has arranged thereon a...
US-6,839,220 Multi-layer barrier allowing recovery anneal for ferroelectric capacitors
A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer...
US-6,838,922 Circuit arrangement for generating non-overlapping clock phases
A circuit arrangement for generating non-overlapping clock phases including a first circuit, a second circuit, and a multiplexer. The first circuit combines two...
US-6,838,917 Circuit configuration for processing data, and method for identifying an operating state
A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship...
US-6,838,746 Semiconductor configuration and method for fabricating the configuration
The invention proposes a semiconductor configuration having a substrate, which has at least one component integrated therein. The substrate has a first main side...
US-6,838,729 Semiconductor component with enhanced avalanche ruggedness
The invention relates to a semiconductor component with enhanced avalanche ruggedness. At the nominal current of this semiconductor component, in the event of an...
US-6,838,724 Transistor array and semiconductor memory configuration fabricated with the transistor array
A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of...
US-6,838,339 Area-efficient stack capacitor
An area-efficient stack capacitor for use in an integrated circuit comprises, in one embodiment, a layer of elemental platinum (Pt) as a bottom electrode, a...
US-6,838,335 Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an...
A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation...
US-6,838,334 Method of fabricating a buried collar
A method of forming a buried collar on the sidewall of a trench in a semiconductor substrate including: (a) providing the trench in the semiconductor substrate,...
US-6,838,216 Photolithographic mask and methods for producing a structure and of exposing a wafer in a projection apparatus
Auxiliary openings are assigned to openings on a mask to be transferred to a wafer. These auxiliary openings have a phase-shifting property, preferably between...
US-6,838,212 Method for producing scatter lines in mask structures for fabricating integrated electrical circuits
In the method according to the invention, scatter lines (2, 3, 4, 5, 6, 7, 8) with a predetermined width are produced, which run at a predetermined distance from...
US-6,836,953 Method of producing a biometric sensor
In a biometric sensor and a method for its production, a sensor chip is provided with connecting contacts in the form of electrically conductive bumps. The...
US-6,836,866 Circuit including a built-in self-test
A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface....
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