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Multi-bank chip compatible with a controller designed for a lesser number
of banks and method of operating
A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a...
Method for recognizing and replacing defective memory cells in a memory
A method for recognizing a defective memory cell in a memory having a plurality of memory cells includes directly comparing predetermined properties of the...
Needle-card adjusting device for planarizing needle sets on a needle card
A needle-card adjusting device for planarizing needle sets on a needle card, in which the needle card is connected to a circuit board used as a contact interface...
Amplifier circuit with offset compensation
An amplifier circuit with offset compensation is particularly suited for a Hall element. In addition to the useful signal demodulation that is normally present...
Memory cell and production method
A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region...
Trench capacitor and method for manufacturing the same
A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first...
Method for forming a trench in a semiconductor substrate
A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is...
Method of forming a gate electrode contact spacer for a vertical DRAM
A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches...
Method for manufacturing a multi-bit memory cell
A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge...
Method for producing a stable bond between two wafers
A method for producing a re-releasable bond between two wafers which is stable at high temperatures and mechanically stable is described. The two wafers to be...
Housing for plug-connected electrical component and method of mounting such
a housing on a printed circuit board
A connector for a plug-connected electrical component, in particular, an optoelectronic transceiver, includes a package having fastening pins for fastening the...
Integrated waveguide arrangement, process for producing an integrated
waveguide arrangement, and waveguide...
The invention explains, inter alia, integrated waveguide arrangements in which a waveguide with glass core and glass sheath is arranged in a waveguide layer...
Semiconductor chip with trimmable oscillator
A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the...
Tri-state driver arrangement
A tri-state driver arrangement has a coupler (2) for the potential-free transmission of signals between an input and an output of the tri-state driver...
Integrated circuit having a test operating mode and method for testing a
multiplicity of such circuits
Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven...
Microelectronic structure, method for fabricating it and its use in a
A microelectronic structure that is suitable, in particular, as part of a storage capacitor includes a semiconductor structure, a barrier structure, an electrode...
Memory module with improved electrical properties
A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of...
Semiconductor storage component with storage cells, logic areas and filling
The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions...
Ferroelectric memory cell with diode structure to protect the ferroelectric
during read operations
A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between...
Mask and method for patterning a semiconductor wafer
A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122)....
Installation for processing wafers
An installation for processing wafers in at least one clean room is described. The installation has a configuration of production units for carrying out...
Method for fabricating a body region for a vertical MOS transistor
arrangement having a reduced on resistivity
A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the...
Process flow for two-step collar in DRAM preparation
In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing...
Process for etching bismuth-containing oxide films
A process is described for etching oxide films containing at least one bismuth-containing oxide, in particular a ferroelectric bismuth-containing mixed oxide. A...
Packaging system with a tool for enclosing electronic components, and
method of populating a carrying belt
A packaging system and a method of populating a transport belt with a tool for enclosing electronic components in a carrying belt, is described. For this...
Method for designing circuits with sections having different supply
In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being...
Microcontroller with flexible interface to external device
A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group...
Emulator chip package that plugs directly into the target system
The present invention relates to electronic packaging and a method for manufacturing the same. According to an embodiment of the present invention, an emulator...
Synchronized data capturing circuits using reduced voltage levels and
A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized...
Sensing amplifier with single sided writeback
A method of transferring data to a memory storage cell that is attached to a first bitline. The method includes passing a charge representative of data from a...
Semiconductor memory device and test method thereof using row compression
A circuit and method for testing a semiconductor memory device using a row compression test mode is provided. The testing circuit includes at least one equalizer...
Temperature sensor and circuit configuration for controlling the gain of an
A temperature sensor has a first FET transistor circuit, whose operating point is located at the temperature-independent point, and a second FET transistor...
Multiple finger off chip driver (OCD) with single level translator
A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the...
Current generating device with reduced switching time from an energy saving
A current generating device is characterized in that it is configured for, in response to a predetermined event, temporarily impresses a current, which is...
Semiconductor component with a charge compensation structure and associated
A semiconductor component includes a charge compensation structure wherein locations with a maximum local field strength are positioned in a compensation edge...
Self-aligned buried strap process using doped HDP oxide
The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive...
High aspect ratio high density plasma (HDP) oxide gapfill method in a lines
and space pattern
A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active...
Method and configuration for verifying a layout of an integrated circuit
and application thereof for...
With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in...
Power management and control for a microcontroller
A power management system for a microcontroller. The power management system includes a power management state machine for controlling a power mode of a central...
Dual band fet mixer
A dual band mixer has a common node for at least one radio frequency input and an intermediate frequency output. The dual band mixer also has a first transistor...
Integrated memory having a memory cell array with a plurality of segments
and method for operating the...
An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different...
Partial refresh for synchronous dynamic random access memory (SDRAM)
A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of...
Memory arrangement with selectable memory sectors
In order to achieve a maximally space-saving configuration of a matricial memory arrangement (1), for example in the form of a non-volatile flash memory, which...
Circuit configuration for producing a switching signal for a
current-controlled switch-mode power supply
A circuit configuration for generating a switching signal for a current controlled switched mode power supply includes a transformer with windings, a controlled...
Module unit for memory modules and method for its production
The invention relates to a module unit for memory modules and to a method for producing the module unit. A module unit of this type has at least one main module...
Two-stage operational amplifier
A two-stage operational amplifier has an input stage and a downstream output stage. In this configuration, the magnitude of a first supply potential which...
Circuit configuration for setting the operating point of a radiofrequency
transistor and amplifier circuit
An amplifier circuit with a radiofrequency transistor has a circuit for setting the operating point. The setting circuit provides a base current for the...
Apparatus for applying a semiconductor chip to a carrier element with a
A method and an apparatus are described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like...
Semiconductor component having double passivating layers formed of two
passivating layers of different...
A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer...
Circuit configuration for load-relieved switching
A circuit configuration for load-relieved switching has a bridge circuit with at least two controllable power switches, whose controlled paths are arranged in...