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Patent # Description
US-6,684,124 Method for controlling a processing device for a sequential processing of semiconductor wafers
While a first leading semiconductor wafer (11) already processed in a process appliance (1) and belonging to a batch is being measured in a microscope measuring...
US-6,683,486 Low voltage shifter with latching function
A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage...
US-6,683,479 Multiphase comparator
A multiphase comparator circuit includes a first differential stage; a first switching arrangement for connecting an output of the first differential stage to an...
US-6,683,374 Electronic component and process for producing the electronic component
An electronic component has at least a first semiconductor chip module, a second semiconductor chip module, and a substrate to accommodate the semiconductor chip...
US-6,683,328 Power semiconductor and fabrication method
A power semiconductor containing an anode disposed on either a top side or a bottom side is described. A cathode is disposed on the side that is unoccupied by...
US-6,683,009 Method for local etching
A method is described for local etching of surfaces. The method includes the steps of providing a surface, providing an etchant, and providing a device for...
US-6,682,398 Method for characterizing the planarizing properties of an expendable material combination in a...
A method for characterizing planarizing properties of a selected expendable material combination in a chemical-mechanical polishing process includes steps of:...
US-6,682,231 Optical subassembly and related methods for aligning an optical fiber with a light emitting device
An optical subassembly for aligning an optical fiber with a light emitting device includes a fiber optic stub mounted in a ferrule and a v-groove device coupled...
US-6,680,980 Supporting ME2PRML and M2EPRML with the same trellis structure
A Viterbi trellis is provided which allows for implementation of either an EPRML type channel or an E2PRML type channel using a single trellis structure....
US-6,680,857 Unit-architecture with implemented limited bank-column-select repairability
Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line...
US-6,680,503 Field-effect transistor structure with an insulated gate
The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and...
US-6,680,500 Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers
A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a...
US-6,680,151 Alternating phase mask
An alternating phase mask is described in which a propagation of a T phase conflict which occurs in the case of a T pattern structure is avoided by producing a...
US-6,677,813 Integrated circuit for receiving a clock signal, particularly for a semiconductor memory circuit
An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A...
US-6,677,806 Charge pump for generating high voltages for semiconductor circuits
The charge pump generates high voltages for integrated semiconductor circuits. The charge pump has a plurality of pump stages with at least one power transistor...
US-6,677,770 Programmable test socket
A test socket for a semiconductor device includes a guide plate operable to receive the semiconductor device and to maintain electrical terminals of the...
US-6,677,745 Test apparatus for parallel testing a number of electronic components and a method for calibrating the test...
A method for calibrating a test apparatus for parallel testing of a number of semiconductor memories, to a time-critical parameter, in which the components are...
US-6,677,635 Stacked MIMCap between Cu dual damascene levels
A semiconductor device includes a structure composed of a first inter-level-dielectric with an embedded first Cu dual damascene level. A dielectric is coated on...
US-6,677,630 Semiconductor device having ferroelectric film and manufacturing method thereof
First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor...
US-6,677,218 Method for filling trenches in integrated semiconductor circuits
A method in which a recess is formed in the surface of a semiconductor substrate and a material is grown on the inner wall of the recess, includes the steps of...
US-6,677,205 Integrated spacer for gate/source/drain isolation in a vertical array structure
Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two...
US-6,677,197 High aspect ratio PBL SiN barrier formation
In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of...
US-6,674,813 Integrated circuit for detecting a received signal and circuit configuration
In order to detect a received signal quickly and reliably, an integrated circuit for detecting a received signal has an intermediate frequency detector which...
US-6,674,774 Chopped laser driver for low noise applications
A circuit (10) for driving a laser diode (12) includes a fixed current source (14), a programmable current source (16), a differential output driver (18), a...
US-6,674,684 Multi-bank chip compatible with a controller designed for a lesser number of banks and method of operating
A memory chip and a method of operating a chip with a number of banks of memory to be backward compatible with a controller designed to operate a chip having a...
US-6,674,674 Method for recognizing and replacing defective memory cells in a memory
A method for recognizing a defective memory cell in a memory having a plurality of memory cells includes directly comparing predetermined properties of the...
US-6,674,627 Needle-card adjusting device for planarizing needle sets on a needle card
A needle-card adjusting device for planarizing needle sets on a needle card, in which the needle card is connected to a circuit board used as a contact interface...
US-6,674,322 Amplifier circuit with offset compensation
An amplifier circuit with offset compensation is particularly suited for a Hall element. In addition to the useful signal demodulation that is normally present...
US-6,674,132 Memory cell and production method
A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region...
US-6,674,113 Trench capacitor and method for manufacturing the same
A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first...
US-6,673,693 Method for forming a trench in a semiconductor substrate
A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is...
US-6,673,686 Method of forming a gate electrode contact spacer for a vertical DRAM device
A gate electrode contact spacer (144) for a vertical DRAM device (100) and a method for forming the same. Memory cells (118) are formed within deep trenches...
US-6,673,677 Method for manufacturing a multi-bit memory cell
A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge...
US-6,673,189 Method for producing a stable bond between two wafers
A method for producing a re-releasable bond between two wafers which is stable at high temperatures and mechanically stable is described. The two wafers to be...
US-6,672,901 Housing for plug-connected electrical component and method of mounting such a housing on a printed circuit board
A connector for a plug-connected electrical component, in particular, an optoelectronic transceiver, includes a package having fastening pins for fastening the...
US-6,671,439 Integrated waveguide arrangement, process for producing an integrated waveguide arrangement, and waveguide...
The invention explains, inter alia, integrated waveguide arrangements in which a waveguide with glass core and glass sheath is arranged in a waveguide layer...
US-6,671,221 Semiconductor chip with trimmable oscillator
A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the...
US-6,670,827 Tri-state driver arrangement
A tri-state driver arrangement has a coupler (2) for the potential-free transmission of signals between an input and an output of the tri-state driver...
US-6,670,802 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits
Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven...
US-6,670,668 Microelectronic structure, method for fabricating it and its use in a memory cell
A microelectronic structure that is suitable, in particular, as part of a storage capacitor includes a semiconductor structure, a barrier structure, an electrode...
US-6,670,665 Memory module with improved electrical properties
A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of...
US-6,670,662 Semiconductor storage component with storage cells, logic areas and filling structures
The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions...
US-6,670,661 Ferroelectric memory cell with diode structure to protect the ferroelectric during read operations
A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between...
US-6,670,646 Mask and method for patterning a semiconductor wafer
A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122)....
US-6,670,568 Installation for processing wafers
An installation for processing wafers in at least one clean room is described. The installation has a configuration of production units for carrying out...
US-6,670,244 Method for fabricating a body region for a vertical MOS transistor arrangement having a reduced on resistivity
A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the...
US-6,670,235 Process flow for two-step collar in DRAM preparation
In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing...
US-6,669,857 Process for etching bismuth-containing oxide films
A process is described for etching oxide films containing at least one bismuth-containing oxide, in particular a ferroelectric bismuth-containing mixed oxide. A...
US-6,668,524 Packaging system with a tool for enclosing electronic components, and method of populating a carrying belt
A packaging system and a method of populating a transport belt with a tool for enclosing electronic components in a carrying belt, is described. For this...
US-6,668,356 Method for designing circuits with sections having different supply voltages
In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being...
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