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Patent # Description
US-6,816,876 Apparatus and method for modifying an M-sequence with arbitrary phase shift
An embodiment of the invention described in the specification and drawings is an apparatus and method of generating a phase-shifted maximum length pseudo-random...
US-6,816,432 Integrated semiconductor circuit having transistors that are switched with different frequencies
It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage....
US-6,816,406 Magnetic memory configuration
A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed...
US-6,816,328 Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel
Systems and methods for reading information stored on a magnetic medium are described. Data symbols are generated from a signal encoded at a baud rate with data...
US-6,816,094 Circuit configuration for the bit-parallel outputting of a data word
A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the...
US-6,816,024 Oscillator circuit with switchable compensated amplifiers
An oscillator circuit is specified, having an LC resonator, to which two or more current paths are connected, which are connected in parallel with one another...
US-6,815,803 Multiple chip semiconductor arrangement having electrical components in separating regions
A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted...
US-6,815,769 Power semiconductor component, IGBT and field-effect transistor
A trench power semiconductor component, in particular an IGBT, has an electrode (4) in a trench (3) that is laterally divided into a section (10) that serves as...
US-6,815,643 Semiconductor device with temperature regulation
A semiconductor device is described in which an integrated circuit executes dummy operating cycles in order to generate heat if the temperature of the ...
US-6,815,367 Elimination of resist footing on tera hardmask
A process of eliminating resist footing on a hardmask when preparing a semiconductor wafer stack, comprising: a) depositing a layer of hardmask material on a...
US-6,815,364 Tungsten hard mask
Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of...
US-6,815,317 Method to perform deep implants without scattering to adjacent areas
A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the...
US-6,815,248 Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed...
A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114),...
US-6,815,244 Methods for producing a thermoelectric layer structure and components with a thermoelectric layer structure
A method produces a thermoelectric layer structure on a substrate and the thermoelectric layer structure has at least one electrically anisotropically conductive...
US-6,815,234 Reducing stress in integrated circuits
A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress...
US-6,815,224 Low-temperature processing of a ferroelectric strontium bismuth tantalate layer, and fabrication of...
In a method for producing ferroelectric strontium bismuth tantalate having the composition Sr.sub.x Bi.sub.y Ta.sub.2 O.sub.9 (SBT) or Sr.sub.x Bi.sub.y (Ta,...
US-6,813,748 System and method for enabling a vendor mode on an integrated circuit
A system and method for enabling a vendor mode on an integrated circuit. A method is disclosed for applying a potential to a no-connect pin, whose function is...
US-6,813,744 ACS unit for a viterbi decoder
An ACS unit is proposed for a Viterbi decoder, which, in order to determine the path metrics of two states of a time step in a trellis diagram, compares the...
US-6,813,695 Memory access method and circuit configuration
A cache memory serves for accelerating accesses to an external memory of a microprocessor. Instead of an actually occurring hit event, a cache miss is signaled...
US-6,813,217 Integrated memory having an accelerated write cycle
An integrated memory has a respective terminal for a clock signal and a data clock signal and also a data terminal. For a write operation, the memory accepts a...
US-6,813,200 Circuit configuration for reading out a programmable link
A circuit configuration for reading out a programmable link enables programming the programmable link in addition to reading out the programmed value into a...
US-6,813,193 Memory device and method of outputting data from a memory device
A method of outputting data from a memory device, such as a dynamic random access memory, is disclosed. The method comprises the steps of providing an integrated...
US-6,813,181 Circuit configuration for a current switch of a bit/word line of a MRAM device
A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional...
US-6,812,880 Analog-to-digital converter and method for converting an analog signal into a digital signal
The invention relates to an analog-to-digital converter (301), comprising several comparators (303) and a reference network, said reference network having...
US-6,812,877 Apparatus for converting a digital value into an analog signal
An apparatus converts a digital value including "a" bits into an analog signal and has 2.sup.b D/A converters. Here, b is an integer number that is greater than...
US-6,812,801 Crystal oscillator circuit having capacitors for governing the resonant circuit
A crystal oscillator circuit has capacitors that govern the resonant circuit and are designed such that they can be connected and disconnected, for frequency...
US-6,812,689 Method and device for offset-voltage free voltage measurement and adjustment of a reference voltage source of...
A method and device for measuring voltage of an internal reference voltage source of an integrated semiconductor circuit, in particular, a DRAM, including the...
US-6,812,684 Bandgap reference circuit and method for adjusting
The invention relates to a method for adjusting a BGR circuit. In a first adjustment step, an offset adjustment of a voltage differential amplifier is performed...
US-6,812,524 Field effect controlled semiconductor component
A semiconductor component includes first and second connection zones formed in a semiconductor body, a channel zone surrounding the second connection zone in the...
US-6,812,162 Rapid deposition of borosilicate glass films
A method for rapidly depositing a borosilicate glass film on a semiconductor wafer includes controlling the pressure within the chamber, introducing oxygen into...
US-6,812,141 Recessed metal lines for protective enclosure in integrated circuits
Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be...
US-6,812,130 Self-aligned dual damascene etch using a polymer
A method for forming a dual damascene structure for a semiconductor device, in accordance with the present invention, includes providing conductive regions on a...
US-6,812,094 Method for roughening a surface of a semiconductor substrate
A method for roughening a surface of a semiconductor substrate includes the steps of placing the substrate in a furnace, introducing Oxygen and an inert gas,...
US-6,812,092 Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line...
A Dynamic Random Access Memory is fabricated in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which...
US-6,812,091 Trench capacitor memory cell
An improved sub 8F.sup.2 memory cell is disclosed. The sub 8F.sup.2 cell includes a shallow transistor trench in which a buried portion of the transistor occupies.
US-6,810,240 Analog multiplier
The analog multiplier has a MOS input stage. This makes it possible to increase the linearity range of the multiplier. In a development, a cascode circuit having...
US-6,810,174 Optical filter and optical filtering method
An optical signal alternately traverses a total of n couplers and n-1 DGD units, arranged therebetween, with a differential group delay between two signal modes....
US-6,809,980 Limiter for refresh signal period in DRAM
The invention relates to a device (10) for outputting a refresh signal for a memory cell of a semiconductor memory device, the device (10) comprising: a...
US-6,809,978 Implementation of a temperature sensor to control internal chip voltages
A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit,...
US-6,809,972 Circuit technique for column redundancy fuse latches
Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of...
US-6,809,914 Use of DQ pins on a ram memory chip for a temperature sensing protocol
A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit that has a data pin, generating a temperature data...
US-6,809,894 Method and apparatus for handling end of data processing in a data storage device
A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write...
US-6,809,800 Apparatus for patterning a semiconductor wafer
An apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148)...
US-6,809,601 Phase detector for a delay locked loop and delay locked loop with the phase detector
A phase detector for a delay locked loop with a delay unit that delays a periodic clock signal by a settable delay, has a first input for the periodic clock...
US-6,809,510 Configuration in which wafers are individually supplied to fabrication units and measuring units located in a...
A configuration for treating wafers in at least one clean room includes a configuration of production units and measuring units that receive wafers via a...
US-6,809,379 Field effect transistor and method for producing a field effect transistor
The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a...
US-6,809,361 Magnetic memory unit and magnetic memory array
A magnetic memory unit having a first magnetizable electrode, a second magnetizable electrode, and at least one nanotube arranged between the electrodes in a...
US-6,809,019 Method for producing a semiconductor structure, and use of the method
A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are...
US-6,809,005 Method to fill deep trench structures with void-free polysilicon or silicon
The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a...
US-6,807,514 Apparatus for monitoring the proper operation of components of an electrical system carrying out the same or...
The apparatus monitors several system components for proper operation. Each of the system components to be monitored is assigned at least one dedicated...
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