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Patent # Description
US-6,751,449 Circuit configuration for band changeover in high-frequency receivers
Conventional circuit configurations for range changeover between different bands (UHF, VHF) in television receivers utilize MOS tetrodes whose operating point...
US-6,751,263 Method for the orthogonal frequency division modulation and demodulation
In orthogonal frequency division modulation, use is made of the fact that the individual carriers which are transmitted on the principle of frequency...
US-6,751,145 Volatile semiconductor memory and mobile device
The volatile semiconductor memory is constructed from a plurality of memory segments. The information stored in the memory cells must be regularly reconditioned....
US-6,751,140 Method for testing integrated semiconductor memory devices
In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the...
US-6,751,135 Method for driving memory cells of a dynamic semiconductor memory and circuit configuration
A dynamic semiconductor memory has memory cells disposed in a cell field. The memory cells are connected to master word lines by way of a word line driver for...
US-6,751,130 Integrated memory device, method of operating an integrated memory, and memory system having a plurality of...
An integrated memory has a selection circuit for setting a selectable latency--relative to a clock signal between a beginning of a read access and the provision...
US-6,751,077 ESD protection configuration for signal inputs and outputs with overvoltage tolerance
An ESD protective configuration for signal inputs and outputs is described. The inventive configuration is provided with an overvoltage tolerance, especially in...
US-6,750,697 Configuration and method for switching transistors
A configuration and a method for the simultaneous switching of transistors connected in series, one from the on state to the off state and the other from the off...
US-6,750,671 Apparatus for testing semiconductor devices
An apparatus for testing wafer-level semiconductor devices, in particular memory chips in which a tunable light source radiates energy onto the semiconductor...
US-6,750,670 Integrated test circuit
An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted...
US-6,750,554 Mark configuration, wafer with at least one mark configuration and method for the fabrication of at least one...
A mark configuration is provided for the orientation and/or determination of the relative position of a substrate and/or of layers on the substrate during a...
US-6,750,509 DRAM cell configuration and method for fabricating the DRAM cell configuration
A DRAM cell configuration is described in which a memory cell in each case has a storage capacitor and a read-out transistor. For connecting to the read-out...
US-6,750,483 Silicon-germanium bipolar transistor with optimized germanium profile
A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter...
US-6,750,317 Material and additive for highly crosslinked chemically and thermally stable polyhydroxyamide polymers
Polyhydroxyamides are polymerized to form highly-crosslinked, temperature-stable polymers. The polyhydroxyamides include as their central, parent structure a...
US-6,750,140 Process for producing contact holes on a metallization structure
The present invention relates to a process for producing contact holes on a metallization structure, which can be used, for example, to produce electrical...
US-6,750,129 Process for forming fusible links
A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding...
US-6,750,122 Semiconductor device formed with an oxygen implant step
A method of forming a semiconductor structure (see e.g., FIG. 3) includes forming a silicon (e.g., polysilicon) layer 14. The silicon layer 14 is patterned and...
US-6,750,115 Method for generating alignment marks for manufacturing MIM capacitors
A method of manufacturing a semiconductor device, comprising depositing an insulating layer over a workpiece, and defining a pattern for at least one alignment...
US-6,750,113 Metal-insulator-metal capacitor in copper
A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 .mu.m) with a bottom etch stop layer, a composite...
US-6,750,112 Method of forming a bitline and a bitline contact, and dynamic memory cell including a bitline and bitline made...
A method of forming a bitline and a bitline contact and a dynamic random access memory (DRAM) cell array includes the following steps. The bitline and the...
US-6,750,111 Method for fabricating a trench capacitor
A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper...
US-6,750,098 Integrated semiconductor memory and fabrication method
In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface...
US-6,750,096 Trench capacitor with buried plate and method for its production
A method for forming a trench with a buried plate includes the steps of forming a trench in a substrate, depositing a non-doped silicate oxide in the trench and...
US-6,750,095 Integrated circuit with vertical transistors
A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a...
US-6,749,716 Apparatus for assessing a silicon dioxide content
An apparatus for assessing a silicon dioxide content of a phosphoric acid bath for etching silicon nitride and a system for etching silicon nitride bath utilize...
US-6,748,153 Optical fiber systems
An optical fiber system that enables direct board-to-board optical communication is described. The optical fiber system does not require data transmission...
US-6,747,891 Circuit for non-destructive, self-normalizing reading-out of MRAM memory cells
A circuit is provided for the non-destructive, self-normalizing reading-out of MRAM memory cells. Accordingly, read currents of a memory cell are normalized by...
US-6,747,505 Circuit configuration for controlling a load with reduced noise emission
A circuit configuration for controlling a load with reduced noise emission is proposed. The circuit contains a switching device that is connected in series with...
US-6,747,496 DLL-(delay-locked-loop) circuit
The present invention provides a Delay Locked Loop circuit having: a delay device for generating at least one delayed clock signal from an input clock signal; a...
US-6,747,495 Low jitter analog-digital locker loop with lock detection circuit
A digital phase detector compares the output clock signal of the oscillator with the reference clock signal, an analog phase detector, and a lock detection...
US-6,747,486 Comparator
A comparator includes an adjustable offset and particularly dimensioned and configured components. The particular configuration and dimensioning of the...
US-6,747,440 Voltage regulator circuit for smart card ICs
The circuit contains a series regulator with an FET. A capacitor and a further FET, which is provided as a transfer gate and is driven by the POR signal, are...
US-6,747,257 Monolithic optical pickup and an assembly including the pickup with laser source(s) and optical detector(s)
A monolithic optical pickup has all passive optical elements aligned during fabrication, thereby requiring no alignment during the assembly of a system utilizing...
US-6,747,230 Method and device for sorting wafers
A method and a device for sorting wafers from an initial state into an end state. The wafers are at least partly identifiable as elements of a finite sequence...
US-6,746,880 Method for making electrical contact with a rear side of a semiconductor substrate during its processing
A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the...
US-6,746,877 Encapsulation of ferroelectric capacitors
A ferroelectric capacitor encapsulation method for preventing hydrogen damage to electrodes and ferroelectric material of the capacitor. In general terms, the...
US-6,746,828 Process for structuring a photoresist layer
A method for structuring a photoresist layer includes the steps of providing a substrate on which a photoresist layer has been applied at least in some areas....
US-6,746,827 Process for structuring a photoresist layer
A method for structuring a photoresist layer includes the steps of providing a substrate on which a photoresist layer has been applied at least in some areas....
US-6,746,821 Method of structuring a photoresist layer
A method structures a chemical amplification photoresist layer, in which a photoresist layer of the chemically amplified type is brought into contact, before or...
US-6,745,637 Self-supporting adaptable metrology device
A metrology device is described which is couplable to a load port of a semiconductor product handling and/or processing tool. The tool encloses a ...
US-6,745,380 Method for optimizing and method for producing a layout for a mask, preferably for use in semiconductor...
A method of producing a layout for a mask for use in semiconductor production includes a two-stage, iterative optimization of the position of scatter bars in...
US-6,745,342 Universal serial bus transceiver shortcut protection
A Universal Serial Bus interface including a USB device controller coupled by way of a shortcut protection circuit to a USB transceiver. The shortcut protection...
US-6,744,686 Semiconductor memory module with low current consumption
A semiconductor memory module with a changeover device by which an internal voltage supply circuit can be switched on or off in a simple manner. The changeover...
US-6,744,682 Semiconductor memory with jointly usable fuses
A semiconductor memory apparatus includes a first and second memory bank. Each of these memory banks has a plurality of row and column lines and at least one...
US-6,744,665 Memory cell configuration
A memory cell configuration has a nonvolatile memory that can be latched by a latching element. The nonvolatile memory is latched by activating a copy of the...
US-6,744,662 Magnetoresistive memory (MRAM)
The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way...
US-6,744,304 Circuit for generating a defined temperature dependent voltage
An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant...
US-6,744,279 Data register with integrated signal level conversion
Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which...
US-6,744,271 Internal generation of reference voltage
An integrated circuit (IC) configured for being connected to an external reference voltage uses an IC reference voltage to determine the logic levels of signals...
US-6,744,241 Method for driving a switch in a switch-mode converter, and a drive circuit for driving a switch
The present invention relates to a method and to a drive circuit for driving a switch in a switch-mode converter that has input terminals for supplying an input...
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