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Patent # Description
US-6,718,487 Method for high speed testing with low speed semiconductor test equipment
A method for testing semiconductor memories, in accordance with the invention includes providing a tester having a plurality of data channels. The tester...
US-6,718,020 Switchable POTS splitter
Switchable POTS-splitter for separating a voice signal from a data signal having a high pass filter for the data signal and a low pass filter for the voice...
US-6,717,972 VCSEL with monolithically integrated photodetector
A VCSEL has an active layer, a photodetector in one of the DBR gratings and with a radiation-absorbing layer that is arranged in an antinode of a laser mode. The...
US-6,717,886 Control circuit for an S-DRAM
Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value;...
US-6,717,870 Method for assessing the quality of a memory unit
Assessing the burn-in of faulty memory units on a wafer includes detecting only those defective memory cells that lie along control lines in the case of which...
US-6,717,843 Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type
A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage...
US-6,717,832 Method for data communication between a plurality of semiconductor modules and a controller module and...
A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory...
US-6,717,788 Temperature-protected semiconductor circuit configuration
A temperature-protected semiconductor circuit configuration that has an integrated switching unit. The switching unit is formed of a semiconductor switch, a...
US-6,717,503 Coil and coil system for integration into a micro-electronic circuit and microelectronic circuit
The coil and coil system is provided for integration in a microelecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is...
US-6,717,447 Delay adjustment circuit
A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a...
US-6,717,437 Semiconductor module
The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on...
US-6,717,436 Reconfigurable gate array
The invention relates to an FPGA (field programmable gate array) with a plurality of functional blocks. An interface enables data and address communication...
US-6,717,431 Method for semiconductor yield loss calculation
A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the...
US-6,717,205 Vertical non-volatile semiconductor memory cell and method for manufacturing the memory cell
A vertical non-volatile semiconductor memory cell and an associated manufacturing method in which a trench extension, which has a third dielectric layer and a...
US-6,716,748 Reaction chamber for processing a substrate wafer, and method for processing a substrate using the chamber
A reaction chamber for processing a substrate wafer is described. The reaction chamber has a wafer holder for receiving the substrate wafer, a convection plate,...
US-6,716,734 Low temperature sidewall oxidation of W/WN/poly-gatestack
In a method of making a W/WN/Poly-Gatestack, the improvement of providing low temperature sidewall oxidation to affect less outdiffusion of dopant implants near...
US-6,716,720 Method for filling depressions on a semiconductor wafer
A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of...
US-6,716,712 Process for producing two differently doped adjacent regions in an integrated semiconductor
During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for...
US-6,716,678 Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive...
A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application...
US-6,716,659 Method and apparatus for shaping semiconductor surfaces
A method and an apparatus for shaping semiconductor surfaces, in which a semiconductor wafer with a surface to be shaped is clamped in-between two plates. In...
US-6,716,643 Method for producing a semiconductor memory element
A method for fabricating a contact hole for a semiconductor memory element. The memory element includes a silicon substrate, an intermediate dielectric layer on...
US-6,715,346 Atomic force microscopy scanning methods
A method of scanning a deep feature using an atomic force microscopy (AFM) tip, which includes: locating and mapping the deep feature with a surface survey scan;...
US-6,715,138 Method for combining logic-based circuit units and memory-based circuit units and circuit arrangement
A method for combining logic-based circuit units and memory-based circuit units in a common circuit arrangement is provided. The different supply voltage swings...
US-6,715,136 Method for simulating an electrical circuit, computer program product, software application, and data carrier
An electrical circuit can be described by a layout and by a network list. A network list has one or more cells each having one or more cell entities. From an...
US-6,715,118 Configuration for generating signal impulses of defined lengths in a module with a bist-function
In the configuration, the module can "learn" one or more time intervals from the external tester and then repeat them internally or compare them to its own...
US-6,715,012 Bus system
The bus system has a bus and a plurality of line sections connected to the bus via respective drivers. The bus with line sections that are not needed can be...
US-6,714,613 Apparatus and method for controlling the sampling clock in a data transmission system
A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation...
US-6,714,603 Asynchronous timing for interpolated timing recovery
A quotient (y.sub.2 -y.sub.0)/(y.sub.3 -y.sub.1) is generated by circuitry where Y.sub.k are asynchronous samples from a sequence of asynchronous samples, the...
US-6,714,418 Method for producing an electronic component having a plurality of chips that are stacked one above the other...
An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first...
US-6,714,397 Protection configuration for schottky diode
A protection device for a Schottky diode is described. The protection device has a cascade circuit with at least two Si-PIN diodes provided parallel to the...
US-6,714,392 Electronic component and utilization of a guard structure contained therein
An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric...
US-6,714,068 Circuit configuration with selectively operating amplifiers
A circuit configuration is configured such that selectively a first amplifier or a second amplifier amplifies signals. The second amplifier is operated depending...
US-6,714,055 Output driver devices
The invention features an output driver device for an integrated circuit that includes an output device having an output terminal for an output signal to be...
US-6,714,029 Contact pin for testing microelectronic components having substantially spherical contacts
In order to test, in particular, BGA (Ball Grid Array) contacts, the free contact pin end is formed as a suction tube in which a reduced pressure that acts on...
US-6,713,884 Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors
An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment...
US-6,713,841 ESD guard structure
An ESD guard structure includes a self-aligned lateral p+/n+ diode serving as the trigger diode. This lateral trigger diode is largely independent of alignment...
US-6,713,802 Magnetic tunnel junction patterning using SiC or SiN
A material that is harder than silicon dioxide is used as a hard mask to pattern the soft layer of an MTJ stack of a magnetic memory device, which increases the...
US-6,713,797 Textured Bi-based oxide ceramic films
A non-volatile memory cell wherein the capacitor comprises a Bi-based metal oxide having a crystallographic texture to produce high switchable polarization.
US-6,713,677 Housing assembly for an electronic device and method of packaging an electronic device
A housing assembly forms a package for an electronic device. The housing assembly has the electronic device, an external carrier and a housing frame. A...
US-6,713,395 Single RIE process for MIMcap top and bottom plates
A method of forming MIM capacitor top (16) and bottom (12) plates, using a first and second resist (18/20) and a single RIE process. A first conductive layer...
US-6,713,364 Method for forming an insulator having a low dielectric constant on a semiconductor substrate
A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second...
US-6,713,236 Lithography method for preventing lithographic exposure of peripheral region of semiconductor wafer
A lithography method for use in the manufacture of semiconductor devices, which prevents lithographic exposure of a periphery region or edge region of a...
US-6,711,091 Indication of the system operation frequency to a DRAM during power-up
A method of using a memory chip includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal...
US-6,711,085 Digital memory circuit having a plurality of segmented memory areas
A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is...
US-6,711,082 Method and implementation of an on-chip self refresh feature
Methods, apparatus, and systems for trimming a periodic self-refresh timing signal of a dynamic random access memory (DRAM) device are described. The ...
US-6,711,081 Refreshing of multi-port memory in integrated circuits
A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh...
US-6,711,080 Evaluation circuit for reading out an information item stored in a memory cell
The invention relates to an evaluation circuit for reading out the information stored in a memory cell, the current (read-out current) carried on a bit line (3)...
US-6,711,072 Digital memory circuit having a plurality of memory areas
A memory circuit contains areas having memory cells. To transfer memory data from/to the memory cells, two-wire local data lines are provided. Each of the local...
US-6,711,065 1 T flash memory recovery scheme for over-erasure
Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates...
US-6,711,047 Test circuit for an analog measurement of bit line signals of ferroelectric memory cells
A test circuit is integrated in a ferroelectric memory component in order to make analog measurements of bit line signals of ferroelectric memory cells. The test...
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