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Patent # Description
US-6,710,887 Testing device and method for establishing the position of a notch or bump on a disk
A testing device is used to establish the position of a notch or bump on a disk. The testing device has: a testing area for positioning at least one disk having...
US-6,710,645 Amplifier circuit with offset compensation, in particular for digital modulation devices
An offset voltage at an output of a differential amplifier is compensated for by a control circuit having a digital setting device. The control circuit has a...
US-6,710,640 Active well-bias transistor for programming a fuse
A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor...
US-6,710,633 Method and arrangement for frequency generation
To generate a target frequency from a basic frequency, a phased signal of the basic frequency and of a phase controllable by a phase clock signal is generated in...
US-6,710,603 Overload protection circuit for line drivers
A detection circuit is described which is configured, in particular, for line drivers for ascertaining the presence of an overshooting of a current flowing...
US-6,710,455 Electronic component with at least two stacked semiconductor chips and method for fabricating the electronic...
An electronic component is formed with at least two semiconductor chips that are disposed on a carrier substrate. Active chip surfaces of the semiconductor chips...
US-6,710,438 Enhanced chip scale package for wire bond dies
A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and...
US-6,710,388 Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric...
A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor...
US-6,709,953 Method of applying a bottom surface protective coating to a wafer, and wafer dicing method
The present invention provides a new backside treatment of the wafer. Trenches are cut into the top surface of the wafer by sawing or etching, and after grinding...
US-6,709,949 Method for aligning structures on a semiconductor substrate
In the three-dimensional integration of integrated circuits, a thinned semiconductor substrate is arranged on a second semiconductor substrate and is...
US-6,709,947 Method of area enhancement in capacitor plates
A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin...
US-6,709,876 Method for detecting removal of organic material from a semiconductor device in a manufacturing process
In a method for removing an organic material from semiconductor devices, at least one semiconductor device is inserted into a so-called piranha bath. Measurement...
US-6,709,874 Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation
A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the...
US-6,709,475 Installation for processing wafers
An installation for processing wafers that includes fabrication units, which are located in a clean room, and includes a supply system for supplying and...
US-6,708,890 Circuit configuration and method for authenticating the content of a memory area
A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile,...
US-6,708,816 Device for handling components
A device for handling components (i.e. chips) is described. The device utilizes a conveyor belt that has crowns or recesses in a frame configuration into which...
US-6,708,559 Direct, non-destructive measurement of recess depth in a wafer
A direct and non-destructive method for measuring recess depth in a semiconductor wafer through use of a solvent, comprising: a) placing a recessed wafer into a...
US-6,708,405 Method for producing an electrically conducting connection
A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact...
US-6,708,270 Programmable unit having on chip debugging support module (OCDS) and reset manager that determines if OCDS...
A programmable unit having an OCDS module and a method for using an external debugger to debug the programmable unit equipped with the OCDS module are described....
US-6,707,746 Fuse programmable I/O organization
Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various...
US-6,707,736 Semiconductor memory device
A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output...
US-6,707,705 Integrated dynamic memory device and method for operating an integrated dynamic memory
In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions--to be performed...
US-6,707,699 Historical information storage for integrated circuits
The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events,...
US-6,707,405 Integrated analog multiplexer
An integrated analog multiplexer with several multiplexer inputs, a multiplexer output, a switch device and a differential amplifier with an inverting and a...
US-6,707,123 EUV reflection mask
In an EUV reflection mask which is set up for region-by-region exposure of a radiation-sensitive layer lying on a semiconductor wafer by means of radiation in...
US-6,707,098 Electronic device and method for fabricating an electronic device
An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied...
US-6,707,086 Method for forming crystalline silicon nitride
In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon...
US-6,707,082 Ferroelectric transistor
In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing...
US-6,706,634 Control of separation between transfer gate and storage node in vertical DRAM
A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation...
US-6,706,616 Method for improving thermal process steps
A method for controlling temperature of a semiconductor wafer in a process chamber includes heating the chamber from a starting temperature to a stabilizing...
US-6,706,588 Method of fabricating an integrated circuit having embedded vertical capacitor
Vertical capacitors are formed in a dielectric by a method that forms first and second electrodes spaced apart by a dielectric and substantially perpendicular to...
US-6,704,676 Method and circuit configuration for identifying an operating property of an integrated circuit
An operating property of the integrated circuit, such as its speed class, value is determined during testing. In order to identify the integrated circuit with a...
US-6,704,243 Apparatus for generating memory-internal command signals from a memory operation command
A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for...
US-6,704,232 Performance for ICs with memory cells
An integrated memory device comprises a multitude of sense amplifiers which output an amplified data signal on a data line. The data line is forced to a...
US-6,704,220 Layout for thermally selected cross-point MRAM cell
A resistive memory device (40) and method of manufacturing thereof including magnetic memory cells (14) having a second magnetic layer (20) including at least a...
US-6,704,219 FeRAM memory and method for manufacturing it
To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the...
US-6,703,844 Method for determining the transit time of electrical signals on printed circuit boards using automatic...
Signal transit times on printed circuit boards which are equipped with all the passive components but without any active components can be determined using...
US-6,703,651 Electronic device having stacked modules and method for producing it
An electronic device having stacked modules and method for producing it are described. Each module has a chip. Each chip is mounted on a stack intermediate...
US-6,703,644 Method for producing a semiconductor configuration
In a method for producing a semiconductor configuration that includes at least two semiconductor elements, at least two differently doped surface regions are...
US-6,703,605 Optoelectronic micromodule
An optoelectronic micromodule (201) comprises an optoelectronic component (204), which is fixed on a main carrier (202) and can emit light in an emission...
US-6,703,567 Conductor track layer structure and prestage thereof
The invention relates to a conductor track layer structure precursor stage with conductor tracks, which are disposed on an electrically insulating substrate with...
US-6,703,190 Method for producing resist structures
A method for creating negative resist structures is described. In the method, a chemically fortified resist is applied to a substrate, dried, irradiated with...
US-6,702,589 Leadless socket for decapped semiconductor device
An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads...
US-6,701,492 Method for the determination of resistances and capacitances of a circuit diagram, which represents an...
From a circuit diagram, an electrically connected circuit diagram network is selected. From a layout representing the circuit diagram, an electrically connected...
US-6,701,473 Electrical circuit and method for testing a circuit component of the electrical circuit
The electrical circuit includes a plurality of circuit components which are connected via a bus. At least one of the circuit components can be tested ...
US-6,701,431 Method of generating a configuration for a configurable spread spectrum communication device
A method of generating a configuration for a configurable spread spectrum communication device is disclosed herein. The method, implemented on a computing device...
US-6,701,204 System and method for finding defective tools in a semiconductor fabrication facility
A system and method for finding a defective tool in a semiconductor fabrication facility is disclosed. When the tools process the wafers, data representing the...
US-6,700,831 Integrated memory having a plurality of memory cell arrays and method for operating the integrated memory
An integrated memory has a plurality of memory cell arrays. The memory cell arrays are in each case assigned a decoder for selecting bit lines and word lines. In...
US-6,700,722 High-speed zero phase restart of a multiphase clock
A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality...
US-6,700,428 Circuit configuration with a controllable current limiting circuit for driving a load
A circuit configuration for driving a load is described. The circuit configuration has a first and a second connecting terminal for connecting the load, a first...
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