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Patent # Description
US-6,770,953 Bipolar transistor
A bipolar transistor is provided in which the product of base-collector capacitance and collector resistance can be reduced through a layout optimization, which...
US-6,770,928 Semiconductor memory with vertical selection transistor
A semiconductor memory having memory cells, each memory cell includes a selection transistor and a trench capacitor. The selection transistor is formed in the...
US-6,770,917 High-voltage diode
A high-voltage diode and a method for producing the high-voltage diode involve only three masking steps. Only three masking steps are required due to the use of...
US-6,770,530 Method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a...
The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A...
US-6,770,526 Silicon nitride island formation for increased capacitance
A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor...
US-6,770,423 Negative resist process with simultaneous development and silylation
The invention relates to a process for producing amplified negative resist structures in which, following exposure and contrasting of the resist in a developing...
US-6,769,065 Access authorization device for controlling access requested by an OCDS module
A program-controlled unit with an on-chip debug support (OCDS) module and a method for debugging a program-controlled unit fitted with the OCDS module by using...
US-6,769,035 Same single board computer system operable as a system master and a bus target
A same single board computer system that is operable as a system master and a bus target and methods of operating the same are described. In one system, a...
US-6,768,826 Delivering data optically to an integrated circuit
A system includes a multi-sided module having a cavity housing a substrate and n photoreceivers located on a side of the substrate and adapted to receive a beam...
US-6,768,770 Transceiver with bidirectional internal interface lines
A transceiver has bidirectional internal interface lines which can be connected to a baseband circuit. The transceiver is switchable by the baseband circuit...
US-6,768,695 Circuit configuration for driving a programmable link
A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a...
US-6,768,693 Integrated dynamic memory with control circuit for controlling a refresh mode of memory cells, and method for...
An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A...
US-6,768,686 Read/write amplifier for a DRAM memory cell, and DRAM memory
A description is given of a DRAM memory (10) having a number of DRAM memory cells (15) which each form one or more memory cell arrays (11). Each memory cell (15)...
US-6,768,668 Converting volatile memory to non-volatile memory
The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile...
US-6,768,667 Semiconductor memory device
A DRAM memory cell having an isolation transistor formed from a bipolar transistor.
US-6,768,191 Electronic component with stacked electronic elements
An electronic component includes stacked electronic elements with external contacts. The external contacts are connected to contact terminal pads of an...
US-6,768,169 Transistor having compensation zones enabling a low on-resistance and a high reverse voltage
A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is...
US-6,768,166 Vertical transistor, memory arrangement and method for fabricating a vertical transistor
A vertical transistor (100) has a source region (103), a drain region (109), a gate region (108), and a channel region (104) between the source region (103) and...
US-6,768,155 Circuit with buried strap including liner
Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such...
US-6,768,150 Magnetic memory
A magnetic memory cell is disclosed. The memory cell includes first conductor and second conductors coupled to first and second electrodes of a magnetic element....
US-6,768,139 Transistor configuration for a bandgap circuit
A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type...
US-6,767,781 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask
A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed....
US-6,767,682 Method for producing quadratic contact holes utilizing side lobe formation
An array of small square contact holes, on the order of magnitude of the exposing light wavelength, are formed by selecting the partial coherence and numerical...
US-6,767,674 Method for obtaining elliptical and rounded shapes using beam shaping
A method of fabricating a mask (316) for patterning a semiconductor wafer. The mask (316) includes elliptical (340) or rounded features formed using an...
US-6,767,581 Process for the deposition of thin layers by chemical vapor deposition
A process for the deposition of thin layers by chemical vapor deposition includes adding an effective amount of nitroxyl radicals of the formula ##STR1## to a...
US-6,767,170 Wafer handling system and wafer handling method
A wafer holder has a set of minimum contact wafer support members predefining support member contacting portions on a planar wafer surface of a wafer. The wafer...
US-6,765,951 Method for estimating the channel impulse response of a mobile radio channel
A method for estimating a channel impulse response of a mobile radio channel is described. The mobile radio channel is accessed over a wide bandwidth by a code...
US-6,765,848 Focus and tracking repeatable runout compensator
A repeatable runout compensator that allows a transducer of a servo system in a storage device employing rotating media to follow the eccentricity on the media...
US-6,765,836 Semiconductor memory with a clock synchronization device having a temperature controlled delay circuit
In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal...
US-6,765,826 Write protection control for electronic assemblies
The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration...
US-6,765,521 Decoding device and smart card having such a decoding device
A decoding device includes a signal-conditioning device for generating an intermediate signal from an input signal, a data register for storing a time section of...
US-6,765,421 Duty-cycle correction circuit
An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for...
US-6,765,419 Dynamic delay line control
A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the...
US-6,765,302 Semiconductor module having a configurable data width of an output bus, and a housing configuration having a...
A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is...
US-6,765,262 Vertical high-voltage semiconductor component
The present invention relates to a high-voltage semiconductor component having a semiconductor substrate of a first conduction type on which a semiconductor...
US-6,765,248 Field effect transistor and fabrication method
A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first...
US-6,764,954 Application of alignment marks to wafer
The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive...
US-6,762,965 Method for integrating imperfect semiconductor memory devices in data processing apparatus
A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective...
US-6,762,958 Semiconductor memory with precharge control
The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation,...
US-6,762,637 Edge-triggered d-flip-flop circuit
The circuit forms an edge-triggered D-Flip-Flop with a master/slave configuration. The master circuit has only one master switch controlled by a clock signal and...
US-6,762,635 Clock generator, particularly for USB devices
In accordance with the USB specifications, an accuracy of 0.25% is required for the data transmission rate. To generate a clock signal that allows this accuracy,...
US-6,762,630 Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated...
An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing...
US-6,762,611 Test configuration and test method for testing a plurality of integrated circuits in parallel
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test...
US-6,762,589 Circuit for charging rechargeable batteries having a combined charging and overvoltage protection circuit
A rechargeable battery unit, which is intended for supplying a voltage to an electrical appliance, is charged by an external charging voltage by a charging...
US-6,762,455 Semiconductor component for high reverse voltages in conjunction with a low on resistance and method for...
A semiconductor component includes a semiconductor body of a first conductivity type which accommodates a space charge region. Semiconductor regions of a second...
US-6,762,447 Field-shield-trench isolation for gigabit DRAMs
A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical...
US-6,762,443 Vertical transistor and transistor fabrication method
In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the...
US-6,762,440 Semiconductor component and corresponding test method
A semiconductor component having a first main terminal, a second main terminal, a gate terminal for controlling the current between the main terminals is...
US-6,762,066 Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure
A method produces a semiconductor structure on a substrate. Then, a protective layer is applied to the semiconductor structure. To fabricate a further...
US-6,762,064 Process for fabrication of a ferrocapacitor
A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric...
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