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Patent # Description
US-6,724,026 Memory architecture with memory cell groups
An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process...
US-6,723,657 Method for fabricating a gate stack in very large scale integrated semiconductor memories
A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and...
US-6,722,793 Optical bidirectional transceiver module having a pin element with integrated WDM filter
An optical bidirectional transceiver module includes a module body having an opening, an inner hollow space and a fiber pin pushed through the opening into the...
US-6,721,904 System for testing fast integrated digital circuits, in particular semiconductor memory modules
The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to...
US-6,721,702 Speech recognition method and device
In a method for interactive voice recognition, a word spoken by a user is analyzed. If no definite assignment to a word of a predetermined vocabulary is...
US-6,721,581 Reprogrammable digital wireless communication device and method of operating same
A digital wireless communication device comprises a software-programmable processor, a heterogeneous reconfigurable multiprocessing logic circuit, and a bus...
US-6,721,377 Method and circuit configuration for resynchronizing a clock signal
A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency...
US-6,721,230 Integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory
An integrated memory including memory cells in a plurality of memory cell blocks, each memory cell block being assigned at least one dedicated data line and a...
US-6,721,219 Method and circuit arrangement for reading out and for storing binary memory cell signals
The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the...
US-6,721,215 Integrated dynamic memory and method for operating it
An integrated dynamic memory includes a memory cell array having memory cells each assigned to one of a plurality of groups. The plurality of groups are divided...
US-6,721,214 Drive circuit and control method
A circuit has a control signal input, a control signal output, a delay element for generating a delay duration, and a control logic circuit. The latter controls...
US-6,721,180 Cooling hood for circuit board
A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the...
US-6,720,896 Analog/digital or digital/analog converter having internal reference voltage selection
An A/D converter or D/A converter has an internal voltage selection device. Several reference voltages are available for selection by the selection device, which...
US-6,720,832 System and method for converting from single-ended to differential signals
A single-ended signal is converted to differential signals with a first device that converts an input current of a single-ended input signal to a voltage, a...
US-6,720,816 Integratable circuit configuration for potential-free signal transmission
A circuit configuration for potential-free signal transmission has a transformer with a primary winding and a secondary winding. A drive circuit is connected...
US-6,720,785 Integrated circuit with test mode, and test configuration for testing an integrated circuit
During a function test on an integrated circuit, the integrated circuit is connected to an automatic test machine. A connection pad provided exclusively just for...
US-6,720,663 Method for manufacturing an integrated memory circuit and an integrated memory circuit
In a method for manufacturing an integrated memory circuit, a semiconductor substrate having a front side and a rear side is provided first. The semiconductor...
US-6,720,616 Trench MOS transistor
A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.
US-6,720,598 Series memory architecture
An IC with a memory array having a series architecture is disclosed. The memory cells of the series group are arranged in pairs in which the capacitors of a...
US-6,720,212 Method of eliminating back-end rerouting in ball grid array packaging
Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal...
US-6,719,205 Carrier element for a semiconductor chip for incorporation into smart cards
A carrier element for a semiconductor chip and in particular for incorporation into smart cards. The carrier element has an encapsulation composition protecting...
US-6,718,487 Method for high speed testing with low speed semiconductor test equipment
A method for testing semiconductor memories, in accordance with the invention includes providing a tester having a plurality of data channels. The tester...
US-6,718,020 Switchable POTS splitter
Switchable POTS-splitter for separating a voice signal from a data signal having a high pass filter for the data signal and a low pass filter for the voice...
US-6,717,972 VCSEL with monolithically integrated photodetector
A VCSEL has an active layer, a photodetector in one of the DBR gratings and with a radiation-absorbing layer that is arranged in an antinode of a laser mode. The...
US-6,717,886 Control circuit for an S-DRAM
Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value;...
US-6,717,870 Method for assessing the quality of a memory unit
Assessing the burn-in of faulty memory units on a wafer includes detecting only those defective memory cells that lie along control lines in the case of which...
US-6,717,843 Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type
A multivalue magnetoresistive read/write memory and method of writing to and reading from such a memory. The invention has, inter alia, one or more storage...
US-6,717,832 Method for data communication between a plurality of semiconductor modules and a controller module and...
A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory...
US-6,717,788 Temperature-protected semiconductor circuit configuration
A temperature-protected semiconductor circuit configuration that has an integrated switching unit. The switching unit is formed of a semiconductor switch, a...
US-6,717,503 Coil and coil system for integration into a micro-electronic circuit and microelectronic circuit
The coil and coil system is provided for integration in a microelecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is...
US-6,717,447 Delay adjustment circuit
A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a...
US-6,717,437 Semiconductor module
The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on...
US-6,717,436 Reconfigurable gate array
The invention relates to an FPGA (field programmable gate array) with a plurality of functional blocks. An interface enables data and address communication...
US-6,717,431 Method for semiconductor yield loss calculation
A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the...
US-6,717,205 Vertical non-volatile semiconductor memory cell and method for manufacturing the memory cell
A vertical non-volatile semiconductor memory cell and an associated manufacturing method in which a trench extension, which has a third dielectric layer and a...
US-6,716,748 Reaction chamber for processing a substrate wafer, and method for processing a substrate using the chamber
A reaction chamber for processing a substrate wafer is described. The reaction chamber has a wafer holder for receiving the substrate wafer, a convection plate,...
US-6,716,734 Low temperature sidewall oxidation of W/WN/poly-gatestack
In a method of making a W/WN/Poly-Gatestack, the improvement of providing low temperature sidewall oxidation to affect less outdiffusion of dopant implants near...
US-6,716,720 Method for filling depressions on a semiconductor wafer
A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of...
US-6,716,712 Process for producing two differently doped adjacent regions in an integrated semiconductor
During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for...
US-6,716,678 Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive...
A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application...
US-6,716,659 Method and apparatus for shaping semiconductor surfaces
A method and an apparatus for shaping semiconductor surfaces, in which a semiconductor wafer with a surface to be shaped is clamped in-between two plates. In...
US-6,716,643 Method for producing a semiconductor memory element
A method for fabricating a contact hole for a semiconductor memory element. The memory element includes a silicon substrate, an intermediate dielectric layer on...
US-6,715,346 Atomic force microscopy scanning methods
A method of scanning a deep feature using an atomic force microscopy (AFM) tip, which includes: locating and mapping the deep feature with a surface survey scan;...
US-6,715,138 Method for combining logic-based circuit units and memory-based circuit units and circuit arrangement
A method for combining logic-based circuit units and memory-based circuit units in a common circuit arrangement is provided. The different supply voltage swings...
US-6,715,136 Method for simulating an electrical circuit, computer program product, software application, and data carrier
An electrical circuit can be described by a layout and by a network list. A network list has one or more cells each having one or more cell entities. From an...
US-6,715,118 Configuration for generating signal impulses of defined lengths in a module with a bist-function
In the configuration, the module can "learn" one or more time intervals from the external tester and then repeat them internally or compare them to its own...
US-6,715,012 Bus system
The bus system has a bus and a plurality of line sections connected to the bus via respective drivers. The bus with line sections that are not needed can be...
US-6,714,613 Apparatus and method for controlling the sampling clock in a data transmission system
A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation...
US-6,714,603 Asynchronous timing for interpolated timing recovery
A quotient (y.sub.2 -y.sub.0)/(y.sub.3 -y.sub.1) is generated by circuitry where Y.sub.k are asynchronous samples from a sequence of asynchronous samples, the...
US-6,714,418 Method for producing an electronic component having a plurality of chips that are stacked one above the other...
An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first...
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