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Patent # Description
US-6,714,613 Apparatus and method for controlling the sampling clock in a data transmission system
A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation...
US-6,714,603 Asynchronous timing for interpolated timing recovery
A quotient (y.sub.2 -y.sub.0)/(y.sub.3 -y.sub.1) is generated by circuitry where Y.sub.k are asynchronous samples from a sequence of asynchronous samples, the...
US-6,714,418 Method for producing an electronic component having a plurality of chips that are stacked one above the other...
An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first...
US-6,714,397 Protection configuration for schottky diode
A protection device for a Schottky diode is described. The protection device has a cascade circuit with at least two Si-PIN diodes provided parallel to the...
US-6,714,392 Electronic component and utilization of a guard structure contained therein
An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric...
US-6,714,068 Circuit configuration with selectively operating amplifiers
A circuit configuration is configured such that selectively a first amplifier or a second amplifier amplifies signals. The second amplifier is operated depending...
US-6,714,055 Output driver devices
The invention features an output driver device for an integrated circuit that includes an output device having an output terminal for an output signal to be...
US-6,714,029 Contact pin for testing microelectronic components having substantially spherical contacts
In order to test, in particular, BGA (Ball Grid Array) contacts, the free contact pin end is formed as a suction tube in which a reduced pressure that acts on...
US-6,713,884 Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors
An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment...
US-6,713,841 ESD guard structure
An ESD guard structure includes a self-aligned lateral p+/n+ diode serving as the trigger diode. This lateral trigger diode is largely independent of alignment...
US-6,713,802 Magnetic tunnel junction patterning using SiC or SiN
A material that is harder than silicon dioxide is used as a hard mask to pattern the soft layer of an MTJ stack of a magnetic memory device, which increases the...
US-6,713,797 Textured Bi-based oxide ceramic films
A non-volatile memory cell wherein the capacitor comprises a Bi-based metal oxide having a crystallographic texture to produce high switchable polarization.
US-6,713,677 Housing assembly for an electronic device and method of packaging an electronic device
A housing assembly forms a package for an electronic device. The housing assembly has the electronic device, an external carrier and a housing frame. A...
US-6,713,395 Single RIE process for MIMcap top and bottom plates
A method of forming MIM capacitor top (16) and bottom (12) plates, using a first and second resist (18/20) and a single RIE process. A first conductive layer...
US-6,713,364 Method for forming an insulator having a low dielectric constant on a semiconductor substrate
A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second...
US-6,713,236 Lithography method for preventing lithographic exposure of peripheral region of semiconductor wafer
A lithography method for use in the manufacture of semiconductor devices, which prevents lithographic exposure of a periphery region or edge region of a...
US-6,711,091 Indication of the system operation frequency to a DRAM during power-up
A method of using a memory chip includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal...
US-6,711,085 Digital memory circuit having a plurality of segmented memory areas
A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is...
US-6,711,082 Method and implementation of an on-chip self refresh feature
Methods, apparatus, and systems for trimming a periodic self-refresh timing signal of a dynamic random access memory (DRAM) device are described. The ...
US-6,711,081 Refreshing of multi-port memory in integrated circuits
A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh...
US-6,711,080 Evaluation circuit for reading out an information item stored in a memory cell
The invention relates to an evaluation circuit for reading out the information stored in a memory cell, the current (read-out current) carried on a bit line (3)...
US-6,711,072 Digital memory circuit having a plurality of memory areas
A memory circuit contains areas having memory cells. To transfer memory data from/to the memory cells, two-wire local data lines are provided. Each of the local...
US-6,711,065 1 T flash memory recovery scheme for over-erasure
Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates...
US-6,711,047 Test circuit for an analog measurement of bit line signals of ferroelectric memory cells
A test circuit is integrated in a ferroelectric memory component in order to make analog measurements of bit line signals of ferroelectric memory cells. The test...
US-6,710,887 Testing device and method for establishing the position of a notch or bump on a disk
A testing device is used to establish the position of a notch or bump on a disk. The testing device has: a testing area for positioning at least one disk having...
US-6,710,645 Amplifier circuit with offset compensation, in particular for digital modulation devices
An offset voltage at an output of a differential amplifier is compensated for by a control circuit having a digital setting device. The control circuit has a...
US-6,710,640 Active well-bias transistor for programming a fuse
A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor...
US-6,710,633 Method and arrangement for frequency generation
To generate a target frequency from a basic frequency, a phased signal of the basic frequency and of a phase controllable by a phase clock signal is generated in...
US-6,710,603 Overload protection circuit for line drivers
A detection circuit is described which is configured, in particular, for line drivers for ascertaining the presence of an overshooting of a current flowing...
US-6,710,455 Electronic component with at least two stacked semiconductor chips and method for fabricating the electronic...
An electronic component is formed with at least two semiconductor chips that are disposed on a carrier substrate. Active chip surfaces of the semiconductor chips...
US-6,710,438 Enhanced chip scale package for wire bond dies
A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and...
US-6,710,388 Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric...
A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor...
US-6,709,953 Method of applying a bottom surface protective coating to a wafer, and wafer dicing method
The present invention provides a new backside treatment of the wafer. Trenches are cut into the top surface of the wafer by sawing or etching, and after grinding...
US-6,709,949 Method for aligning structures on a semiconductor substrate
In the three-dimensional integration of integrated circuits, a thinned semiconductor substrate is arranged on a second semiconductor substrate and is...
US-6,709,947 Method of area enhancement in capacitor plates
A method and structure for increasing the area and capacitance of both trench and planar integrated circuit capacitors uses Si nodules deposited on a thin...
US-6,709,876 Method for detecting removal of organic material from a semiconductor device in a manufacturing process
In a method for removing an organic material from semiconductor devices, at least one semiconductor device is inserted into a so-called piranha bath. Measurement...
US-6,709,874 Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation
A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the...
US-6,709,475 Installation for processing wafers
An installation for processing wafers that includes fabrication units, which are located in a clean room, and includes a supply system for supplying and...
US-6,708,890 Circuit configuration and method for authenticating the content of a memory area
A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile,...
US-6,708,816 Device for handling components
A device for handling components (i.e. chips) is described. The device utilizes a conveyor belt that has crowns or recesses in a frame configuration into which...
US-6,708,559 Direct, non-destructive measurement of recess depth in a wafer
A direct and non-destructive method for measuring recess depth in a semiconductor wafer through use of a solvent, comprising: a) placing a recessed wafer into a...
US-6,708,405 Method for producing an electrically conducting connection
A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact...
US-6,708,270 Programmable unit having on chip debugging support module (OCDS) and reset manager that determines if OCDS...
A programmable unit having an OCDS module and a method for using an external debugger to debug the programmable unit equipped with the OCDS module are described....
US-6,707,746 Fuse programmable I/O organization
Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various...
US-6,707,736 Semiconductor memory device
A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output...
US-6,707,705 Integrated dynamic memory device and method for operating an integrated dynamic memory
In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions--to be performed...
US-6,707,699 Historical information storage for integrated circuits
The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events,...
US-6,707,405 Integrated analog multiplexer
An integrated analog multiplexer with several multiplexer inputs, a multiplexer output, a switch device and a differential amplifier with an inverting and a...
US-6,707,123 EUV reflection mask
In an EUV reflection mask which is set up for region-by-region exposure of a radiation-sensitive layer lying on a semiconductor wafer by means of radiation in...
US-6,707,098 Electronic device and method for fabricating an electronic device
An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied...
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