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Patent # Description
US-6,887,783 Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof
An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is...
US-6,887,777 Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
The present invention provides a method for connecting an integrated circuit to a substrate, which has the following steps: provision of a first electrical...
US-6,887,764 Method for producing a gate structure for an MOS transistor
In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a...
US-6,887,761 Vertical semiconductor devices
A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose...
US-6,887,722 Method for exposing a semiconductor wafer
A method for exposing a semiconductor wafer compensates for the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by...
US-6,887,653 Method for structuring a photoresist layer
A method for structuring a photoresist layer is described. A substrate has a photoresist layer containing a film-forming polymer that has a photo acid generator...
US-6,887,437 Reactor configuration and method for producing it
A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into...
US-6,887,358 Installation for processing wafers
An installation for processing wafers with a plurality of fabrication units and a plurality of measurement units as well as a transport system for transporting...
US-6,887,026 Semiconductor product container and system for handling a semiconductor product container
A system for handling a semiconductor product container contains a handler for transporting and positioning the container. A loading/unloading position requires...
US-6,885,963 Method for testing a program-controlled unit by an external test device
A method described is distinguished by the fact that an external test device brings about the execution, in a program-controlled unit, of a program that...
US-6,885,826 Optical transmitter and method for generating a digital optical signal sequence
An optical transmitter and a method for generating a digital optical signal sequence are provided. The optical transmitter has light transmitters which are...
US-6,885,597 Sensing test circuit
A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read...
US-6,885,443 Drive device for a light-emitting component
A drive device for a light emitting component includes a reference source for generating a power stipulation signal that stipulates a desired power. A correction...
US-6,885,254 Calibration device and method for generating a clock in an integrated circuit
To generate an accurate frequency standard in an integrated circuit, it is proposed to activate a reference oscillator at certain time intervals and to calibrate...
US-6,885,220 Current source circuit
A current source circuit is characterized in that it contains a control device that controls a component of the current source circuit that determines a variable...
US-6,885,077 Schottky diode
A Schottky diode has a Schottky junction formed by a thin metal layer and/or metal silicide layer at the top side of a doped well in a semiconductor body or...
US-6,885,062 MOS transistor device with a locally maximum concentration region between the source region and the drain region
In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in...
US-6,884,703 Manufacturing of a low-noise mos device
At the surface of a substrate a gate oxide layer is produced and is given a dual thickness. A first oxide layer is produced over the surface of a substrate by...
US-6,884,688 Method for producing a MOS transistor and MOS transistor
A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain...
US-6,884,676 Vertical 8F2 cell dram with active area self-aligned to bit line
A memory cell is formed in a memory cell array comprised of a plurality of memory cells arranged in rows and columns. A deep trench structure is formed within a...
US-6,884,639 Semiconductor wafer pod
A semiconductor wafer pod includes a measurement sensor configured within a housing. The sensor faces towards a surface of a wafer being accommodated in the pod....
US-6,884,630 Two-step magnetic tunnel junction stack deposition
Magnetic tunnel junction devices can be fabricated using a two-step deposition process wherein respective portions of the magnetic tunnel junction stack are...
US-6,884,567 Photosensitive formulation for buffer coatings, film containing the photosensitive formulation, and method for...
A photosensitive formulation for high-temperature-resistant photoresists is based on polyhydroxyamides. The photosensitive formulations display a much higher...
US-6,883,381 Acceleration sensor and method for manufacturing an acceleration sensor
An acceleration sensor includes a deflectable pressure measuring diaphragm and a counter-structure, which is deflectable as against the pressure measuring...
US-6,882,633 Method and device for synchronizing a mobile radio receiver with a frame structure of a radio signal
A method for synchronizing a mobile radio receiver with a frame structure of a radio signal received from a specific base station assumes that each base station...
US-6,882,584 Method for operating a semiconductor memory, and semiconductor memory
A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of...
US-6,882,556 Semiconductor memory having a configuration of memory cells
A semiconductor memory has a novel geometry of a memory cell array. Without reducing the distance between storage capacitors that are the most closely adjacent...
US-6,882,554 Integrated memory, and a method of operating an integrated memory
An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined...
US-6,882,202 Multiple trip point fuse latch device and method
A multiple trip point fuse latch device and method is disclosed. Multiple read inputs to a fuse latch enable the altering of the resistive trip point of the fuse...
US-6,882,146 Method and system for determining the orientation of magnetic fields by means of GMR sensors
The invention relates to a method and a system for determining the orientation of an external magnetic field by means of giant magneto-resistor (GMR) sensors. A...
US-6,882,139 Electronic component, tester device and method for calibrating a tester device
An electronic calibration component for calibrating a tester device is described. The calibration component has a signal input, to which a tester channel to be...
US-6,882,132 DC voltage chopper for DC voltage
A DC voltage chopper contains a power switch device with a drive circuit, an LC filter circuit connected in a main circuit of the power switch device, a...
US-6,882,027 Methods and apparatus for providing an antifuse function
Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a...
US-6,882,007 SRAM memory cell, memory cell arrangement and method for fabricating a memory cell arrangement
The invention relates to an SRAM memory cell, a memory cell arrangement and a method for fabricating a memory cell arrangement. The SRAM memory cell has six...
US-6,882,004 Semiconductor component, trench structure transistor, trench MOSFET, IGBT, and field-plate transistor
A semiconductor component has a minimal size and area requirement. The semiconductor component is formed in a trench with wall regions and a bottom region....
US-6,881,914 Apparatus and method for handling, storing and reloading carriers for disk-shaped items, such as semiconductor...
An apparatus for handling, storing and reloading carriers for disk-shaped items, such as semiconductor wafers or CDs, has at least one cleaning unit and at least...
US-6,881,592 Method and device for minimizing multi-layer microscopic and macroscopic alignment errors
A method of aligning a second layer to a first layer of a semiconductor structure by forming a first layer of a wafer having a distinguished feature via a first...
US-6,881,264 Configuration and a method for reducing contamination with particles on a substrate in a process tool
A process tool, preferably a spin coater, includes a set of at least three arms and an adjustable rinse nozzle. The arms lift a substrate, e.g. a semiconductor...
US-6,880,055 Semiconductor memory device
So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area...
US-6,879,949 Current coupling for mixed circuit simulation
Electronic circuits and systems which include digital and analog circuit sections are simulated with a combination of analog and digital simulation. For the...
US-6,879,273 Oversampling in analog/digital and digital/analog converters
The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog...
US-6,878,997 Compensation component and method for fabricating the component
A compensation component, in which a lateral section and, at least at one end of the lateral section, a section that is inclined with respect to the surface of a...
US-6,878,996 MOS power transistor
An integrated MOS power transistors, in particular a lateral PMOS power transistor and a lateral n-DMOS power transistor, in which the bulk node is disposed in a...
US-6,878,965 Test structure for determining a region of a deep trench outdiffusion in a memory cell array
A test structure for determining a doping region of an outer capacitor electrode of a trench capacitor in a memory cell array. The trench capacitors of the...
US-6,878,613 Field-effect transistor having a contact to one of its doping regions, and method for fabricating the transistor
A field-effect transistor is formed with a gate stack, which is patterned by a hard mask and contains a first part of a gate electrode and a second part of the...
US-6,878,604 Semiconductor element comprising a sequence of layers for converting acoustic or thermal signal and electrical...
A semiconductor component is provided having a layer sequence for conversion of acoustic to thermal signals and electrical voltage changes to one another, as...
US-6,878,600 Method for fabricating trench capacitors and semiconductor device with trench capacitors
A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated...
US-6,877,944 Configuration for transporting a semiconductor wafer carrier
For bay type structures of semiconductor wafer transport systems, a configuration includes interbay rail tracks and intrabay rail tracks mounted on each other,...
US-6,877,897 Method for determining the temperature of a memory cell from transistor threshold voltage
The temperature of a semiconductor component is determined by way of a memory cell that includes a transistor and a capacitor. To that end, a signal is...
US-6,876,710 Digitally controlled circuit for reducing the phase modulation of a signal
A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that...
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