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Patent # Description
US-6,805,568 Zipper connector
A connector arrangement comprises first conductor teeth on a first support and second conductor teeth on a second support. A slider is provided for electrically...
US-6,804,851 Holder for semiconductor wafers in a brush-cleaning installation
A holder in a brush-cleaning installation, preferably for combined use in the brush-cleaning and centrifugal-drying process, contains a carrier part from which...
US-6,804,519 Forward link inter-generation soft handoff between 2G and 3G CDMA systems
In a CDMA cellular radiotelephone system, a soft handoff (SHO) is performed when a mobile station communicates with a new inter-generation base station, without...
US-6,804,166 Method and apparatus for operating a semiconductor memory at double data transfer rate
A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a...
US-6,804,165 Latency time switch for an S-DRAM
Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data...
US-6,804,160 Memory device and method of accessing a memory device
A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory...
US-6,804,121 Housing for biometric sensor chips and method for producing the housing
A housing for biometric sensor chips and a method for producing such a housing includes a freely accessible fingerprint checking area on a sensor chip, a mount...
US-6,803,870 Procedure and device for analog-to-digital conversion
During A/D conversion of time-discrete analog input values, a quantizer is used in which an analog quantization error is obtained after every conversion. The...
US-6,803,629 Vertical field-effect transistor with compensation zones and terminals at one side of a semiconductor body
A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second...
US-6,803,627 Reverse-blocking power semiconductor component having a region short-circuited to a drain-side part of a body zone
A reverse-blocking power semiconductor component includes a drift path subdivided into a source-side area and a drain-side area by a region with opposite doping....
US-6,803,618 MRAM configuration having selection transistors with a large channel width
The invention relates to an MRAM configuration that includes a selection transistor connected to several MTJ memory cells. The selection transistor has an...
US-6,803,612 Integrated circuit having electrical connecting elements
On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first...
US-6,803,609 Bipolar high-voltage power component
A bipolar high-voltage power component, in particular an IGBT, includes a semiconductor body on which at least two mutually spaced apart electrodes are provided,...
US-6,803,301 Fuse configuration with modified capacitor border layout for a semiconductor storage device
A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first...
US-6,803,156 Electrostatic damage (ESD) protected photomask
A photomask (8) protected against electrostatic damage and a method of manufacturing such a photomask is disclosed. The photomask (8) comprises a transparent...
US-6,802,712 Heating system, method for heating a deposition or oxidation reactor, and reactor including the heating system
A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for...
US-6,801,757 Circuit configuration for matching an amplifier to a radio-frequency line, and use of the circuit configuration
A circuit for matching an amplifier to a radio-frequency line is described. In order to minimize the number of components required for matching the amplifier to...
US-6,801,471 Fuse concept and method of operation
It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on...
US-6,801,314 Alignment system and method using bright spot and box structure
There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is...
US-6,801,087 Integrated circuit with an analog amplifier
An integrated circuit includes an analog amplifier connected to a terminal pad and has a Miller compensation of a section of the analog amplifier. The Miller...
US-6,801,024 Method of frequency limitation and overload detection in a voltage regulator
A regulated output voltage and an output current are generated by using a switching device for providing the output current and controlling the switching device...
US-6,800,926 Tracking circuit
Tracking circuit for tracking the voltage potential of an insulation well for the insulation of an integrated component (1) embedded in the insulation well, the...
US-6,800,925 Integrated circuit configuration having a structure for reducing a minority charge carrier current
An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and...
US-6,800,898 Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench...
The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first...
US-6,800,893 Semiconductor circuit configuration and associated fabrication method
The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of...
US-6,800,890 Memory architecture with series grouped by cells
An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel....
US-6,800,817 Semiconductor component for connection to a test system
The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor...
US-6,800,407 Method for experimentally verifying imaging errors in photomasks
The method enables determining imaging errors of photomasks for the lithographic structuring of semiconductors. A latent image of the mask is first produced in a...
US-6,799,290 Data path calibration and testing mode using a data bus for semiconductor memories
A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device...
US-6,798,706 Integrated circuit with temperature sensor and method for heating the circuit
A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least...
US-6,798,689 Integrated memory with a configuration of non-volatile memory cells and method for fabricating and for...
An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive...
US-6,798,303 Clock signal generating device
A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished...
US-6,798,272 Shift register for sequential fuse latch operation
A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a...
US-6,798,252 High speed sense amplifier
A high-speed sense current amplifier with a low power consumption for a memory cell, the sense current amplifier having: a first current mirror circuit, which...
US-6,798,234 Apparatus for protecting an integrated circuit formed in a substrate and method for protecting the circuit...
An apparatus for protecting an integrated circuit formed in a substrate and a method for protecting the integrated circuit against reverse engineering includes...
US-6,798,051 Connection of packaged integrated memory chips to a printed circuit board
An interface unit and a printed circuit board configuration includes at least two interface units for linking conventional commercially available packages of...
US-6,798,045 Lead frame, circuit board with lead frame, and method for producing the lead frame
A lead frame is described which has at least one integrated electronic circuit. The integrated electronic circuit is situated in a region of a main area of the...
US-6,798,042 Pin diode and method for fabricating the diode
The invention is a diode having at least one trench in the semiconductor substrate and insulation configured on the surface of the semiconductor substrate so...
US-6,798,040 Power semiconductor switch
An IGBT structure includes successive regions whose conductivities have alternating signs. The structure is dimensioned for punch-through and is provided with...
US-6,798,014 Semiconductor memory cell and semiconductor component as well as manufacturing methods therefore
A semiconductor memory cell with a storage transistor, a selection transistor and a layer structure is provided. The layer structure is formed of at least two...
US-6,798,000 Field effect transistor
A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire...
US-6,797,981 Test wafer and method for producing the test wafer
A test wafer is provided, in particular for use in monitoring inspection installations for semiconductor fabrication that are based on the analysis of scattered...
US-6,797,638 Plasma-etching process for molybdenum silicon nitride layers on half-tone phase masks based on gas mixtures...
A method for etching phase shift layers of half-tone phase masks includes etching a phase shift layer by using a plasma which is obtained from CH.sub.3 F and...
US-6,797,636 Process of fabricating DRAM cells with collar isolation layers
A process of preparing DRAM cells with collar isolation layers that isolate the trench top with vertical cell and active area from the buried plate to eliminate...
US-6,797,613 Process for depositing WSix layers on a high topography with a defined stoichiometry
Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten...
US-6,797,562 Method for manufacturing a buried strap contact in a memory cell
A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In...
US-6,797,236 Design and signal recovery of biomolecular sensor arrays
The present invention provides an apparatus and method of reducing noise associated with biomolecular measurement systems. Sensor detection system noise...
US-6,797,029 Process facility having at least two physical units each having a reduced density of contaminating particles...
In a process facility for producing semiconductor wafers, a third physical unit is configured between two physical units that produce mini environments. The...
US-6,795,840 Method for generating a sequence of random numbers of A 1/f-noise
A computer programmed to process a method for generating a sequence of random numbers of a 1/f noise has the following steps: 1). Determining a constant step...
US-6,795,696 Circuit configuration for filtering a radio-frequency signal
A circuit configuration for filtering a radio-frequency signal, in particular, in tuners for television sets, includes a control signal connection for feeding in...
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