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Patent # Description
US-6,737,856 Circuit configuration for detecting the current in a load transistor
The present invention relates to a circuit arrangement having a load transistor (T1) and a current sensing transistor (T2) coupled to the load transistor (T1),...
US-6,737,748 Stacked via with specially designed landing pad for integrated semiconductor structures
In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are...
US-6,737,695 Memory module having a memory cell and method for fabricating the memory module
A memory module and a method for fabricating the memory module are described. The memory module has a memory cell that is disposed in a vertical trench. The...
US-6,737,692 Method for fabricating a component, and component having a metal layer and an insulation layer
A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and...
US-6,737,689 FEMFET device and method for producing same
The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor...
US-6,737,671 Current measurement circuit and method for voltage regulated semiconductor integrated circuit devices
A current measurement circuit and method for testing a semiconductor device is provided. The method includes the steps of providing a semiconductor integrated...
US-6,737,581 Configuration of a plurality of circuit modules
A circuit configuration for reliably and simply interconnecting circuit modules includes a connection carrier and circuit modules disposed essentially one above...
US-6,736,307 Method for mounting leadframes
The present invention relates to a method for mounting electrical components on leadframes. A conveyor belt is used, having a holder which is attached to the...
US-6,735,742 Method for optimizing a cell layout using parameterizable cells and cell configuration data
A method for optimizing the layout of cells of an integrated circuit includes providing a cell-based network list with references to cell definitions with...
US-6,735,138 Integrated memory using prefetch architecture and method for operating an integrated memory
An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read...
US-6,735,095 Switched-mode power supply with a function for detecting a broken feedback loop
A switched mode power supply includes a primary coil, a switch element, a secondary circuit, and a control circuit. The switch element is wired in series with...
US-6,735,065 Semiconductor module
A semiconductor module includes a housing with at least one semiconductor component that is conductively connected to at least one output line. An integrated...
US-6,735,023 Optoelectronic module and method for its production
An optoelectronic module includes a transmitting and/or receiving element, a support on which the transmitting and/or receiving element is disposed, and a module...
US-6,734,770 Microrelay
A microrelay has a switching part which is pivotably suspended on a substrate and can be moved into two alternative switching states like a rocker, by...
US-6,734,761 Radio-frequency input stage
A radio-frequency input stage is specified and has a radio-frequency coupling element which couples an air interface to the inputs of parallel-connected...
US-6,734,728 RF power transistor with internal bias feed
Conventional broadband RF power amplifiers use a 1/4 wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second 1/4...
US-6,734,708 Controllable current source circuit and a phase locked loop equipped with such a circuit
A controllable current source circuit and a phase locked loop contained such a circuit are disclosed. The current source circuit such a single switched driver...
US-6,734,695 Method and semiconductor component having a device for determining an internal voltage
A method and a semiconductor component are described in which an internal voltage to be measured is divided via a matched voltage divider, and is passed to a...
US-6,734,676 Method and timing circuit for generating a switching or control signal
A method for generating a control signal after a predeterminable period of time is described. The method includes applying a voltage to an inductor at a...
US-6,734,600 Component for forming vertically standing waves of a wavelength
A component has a piezoelectric layer, which is arranged between a first lower electrode and a first upper electrode and also a second lower electrode and a...
US-6,734,520 Semiconductor component and method of producing it
A semiconductor component includes a first layer and at least one adjacent semiconductor layer or metallic layer, which forms a rectifying junction with the...
US-6,734,474 Integrated semiconductor circuit having contact points and configuration having at least two such circuits
For a selection of semiconductor chips stacked on top of one another, the invention includes leading through selection contact points of one chip on a rear side...
US-6,734,459 Semiconductor memory cell
A semiconductor memory cell is formed in a substrate and includes a capacitor, a transistor, and an electrical contact. The transistor includes a doped region...
US-6,734,097 Liner with poor step coverage to improve contact resistance in W contacts
A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given...
US-6,734,095 Method for producing cavities with submicrometer patterns in a semiconductor device using a freezing process liquid
A method for producing cavities, which are patterned in submicrometer dimensions, in a cavity layer of a semiconductor device, is described. In the method, a...
US-6,734,077 Method for fabricating a trench capacitor for a semiconductor memory
A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate....
US-6,734,063 Non-volatile memory cell and fabrication method
Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor...
US-6,734,059 Semiconductor device with deep trench isolation and method of manufacturing same
A semiconductor device and method of making the same is provided having enhanced isolation between the bit line contact and the gate region of the semiconductor...
US-6,734,057 Method of patterning capacitors and capacitors made thereby
A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method...
US-6,733,189 Electrooptical transmitting/receiving module, and method for producing the module
An electrooptical transmitting and/or receiving module has a lead frame and an optoelectronic transducer mounted thereon. The lead frame and the optoelectronic...
US-6,732,855 Conveying element and conveyor means for conveying wafer receptacles, and method
A conveyor element (10) for conveying wafer receptacles between a conveyor (12) and a loading station (11) of a manufacturing system in the semiconductor...
US-6,732,590 Pressure sensor and process for producing the pressure sensor
The invention relates to a pressure sensor with an MEM structure (micro electro mechanical structure), which has a hollow housing in which a semiconductor chip...
US-6,731,882 Leadframe-based optoelectronic bidirectional transmitting and receiving module
The transceiver module has the transmitter and receiver mounted on one side of a leadframe above light passage openings formed therein. A beam deflection...
US-6,731,567 DDR memory and storage method
The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed...
US-6,731,554 2T2C signal margin test mode using resistive element
The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality...
US-6,731,552 Integrated dynamic memory and operating method
An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has...
US-6,731,529 Variable capacitances for memory cells within a cell group
A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the...
US-6,731,443 Total error multiplier for optimizing read/write channel
A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood ("PRML") read/write channel is disclosed. A channel margining...
US-6,731,131 Circuit for an electronic semiconductor module
It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the...
US-6,730,989 Semiconductor package and method
A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted...
US-6,730,982 FBEOL process for Cu metallizations free from Al-wirebond pads
A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning...
US-6,730,930 Memory element and method for fabricating a memory element
A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to...
US-6,730,607 Method for fabricating a barrier layer
A method of fabricating a barrier layer includes oxidizing a silicon-containing substrate to form a substrate oxide layer on the surface of the substrate,...
US-6,730,562 Method of patterning ferroelectric layers
A method for structuring ferroelectric layers on semiconductor substrates retains or regenerates the adherence and breakdown voltage resistance of the...
US-6,730,463 Method for determining and removing phase conflicts on alternating phase masks
A photoresist layer on a substrate wafer is exposed in first sections with a first exposure radiation and in second sections with a second exposure radiation...
US-6,729,775 Electro-optical module with a housing
The electro-optical module has a housing in which a supporting plate provided with at least one optical element, electric circuit elements, and electric...
US-6,729,774 Electro-optical module
An electro-optical module includes a connector and a module body having an electro-optical converter. The connector accommodates one end of a fiber optic...
US-6,728,902 Integrated circuit having a self-test device for carrying out a self-test of the integrated circuit
An integrated circuit includes a self-test device which is provided for executing a self-test of the integrated circuit and which has a control output. A program...
US-6,728,321 Receiving device for angle-modulated signals
A receiving device for angle-modulated signals performs the channel selection in a digital manner rather than an analog manner. A receive signal is preferably...
US-6,728,147 Method for on-chip testing of memory cells of an integrated memory circuit
A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading...
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