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Patent # Description
US-6,806,720 Method of reliability testing
A method of reliability testing is disclosed. A critical breakdown resistance of a device is determined. The test structure is subjected to stress conditions and...
US-6,806,694 Switching regulator with dynamic current limiting and drive circuit for the switching regulator
A switching regulator has a drive circuit, receiving an intermediate circuit input voltage, an output voltage of an intermediate circuit capacitor and an output...
US-6,806,579 Robust via structure and method
A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via...
US-6,806,562 Device with at least one semiconductor component and a printed circuit board and method of establishing an...
A device having a semiconductor component and a printed circuit board are described. The semiconductor component has external contacts and the printed circuit...
US-6,806,555 Semiconductor component and method for fabricating it
A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a...
US-6,806,550 Evaluation configuration for semiconductor memories
An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the...
US-6,806,533 Semiconductor component with an increased breakdown voltage in the edge area
A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an...
US-6,806,344 POLY-O-HYDROXAMIDE, POLYBENZOXAZOLE, AND ELECTRONIC COMPONENT INCLUDING A DIELECTRIC HAVING A BARRIER EFFECT...
Novel poly-o-hydroxyamides can be cyclized to give polybenzoxazoles which have a good diffusion barrier effect with respect to metals. The poly-o-hydroxyamides...
US-6,806,182 Method for eliminating via resistance shift in organic ILD
Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces...
US-6,806,152 Retrograde doped buried layer transistor and method for producing the same
An active transistor area with a retrograde doping area on a substrate in bipolar technology is produced by a method including the following steps: providing a...
US-6,806,124 METHOD FOR REDUCING THE CONTACT RESISTANCE IN ORGANIC FIELD-EFFECT TRANSISTORS BY APPLYING A REACTIVE...
A semiconductor device is fabricated and contains a first body made of an organic semiconductor material and a second body made of an electrically conductive...
US-6,806,121 Interconnect structure for an integrated circuit and corresponding fabrication method
The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1'; B1"), which is composed of a...
US-6,806,106 Bond wire tuning of RF power transistors and amplifiers
A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an...
US-6,806,097 Method for fabricating ferroelectric memory cells
Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a...
US-6,806,096 Integration scheme for avoiding plasma damage in MRAM technology
A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the...
US-6,806,037 Method for producing and/or renewing an etching mask
An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed...
US-6,806,027 CHEMICALLY AMPLIFIED PHOTORESIST AND PROCESS FOR STRUCTURING SUBSTITUENTS USING TRANSPARENCY ENHANCEMENT OF...
Chemically amplified photoresists exhibit increased transparency at a wavelength of 157 nm. The chemically amplified photoresist includes a polymer containing...
US-6,806,008 Method for adjusting a temperature in a resist process
A test reticle having a pad and antenna structures with varying critical dimensions is provided to measure sidewall angles developing in the resist sidewalls of...
US-6,805,568 Zipper connector
A connector arrangement comprises first conductor teeth on a first support and second conductor teeth on a second support. A slider is provided for electrically...
US-6,804,851 Holder for semiconductor wafers in a brush-cleaning installation
A holder in a brush-cleaning installation, preferably for combined use in the brush-cleaning and centrifugal-drying process, contains a carrier part from which...
US-6,804,519 Forward link inter-generation soft handoff between 2G and 3G CDMA systems
In a CDMA cellular radiotelephone system, a soft handoff (SHO) is performed when a mobile station communicates with a new inter-generation base station, without...
US-6,804,166 Method and apparatus for operating a semiconductor memory at double data transfer rate
A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a...
US-6,804,165 Latency time switch for an S-DRAM
Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data...
US-6,804,160 Memory device and method of accessing a memory device
A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory...
US-6,804,121 Housing for biometric sensor chips and method for producing the housing
A housing for biometric sensor chips and a method for producing such a housing includes a freely accessible fingerprint checking area on a sensor chip, a mount...
US-6,803,870 Procedure and device for analog-to-digital conversion
During A/D conversion of time-discrete analog input values, a quantizer is used in which an analog quantization error is obtained after every conversion. The...
US-6,803,629 Vertical field-effect transistor with compensation zones and terminals at one side of a semiconductor body
A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second...
US-6,803,627 Reverse-blocking power semiconductor component having a region short-circuited to a drain-side part of a body zone
A reverse-blocking power semiconductor component includes a drift path subdivided into a source-side area and a drain-side area by a region with opposite doping....
US-6,803,618 MRAM configuration having selection transistors with a large channel width
The invention relates to an MRAM configuration that includes a selection transistor connected to several MTJ memory cells. The selection transistor has an...
US-6,803,612 Integrated circuit having electrical connecting elements
On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first...
US-6,803,609 Bipolar high-voltage power component
A bipolar high-voltage power component, in particular an IGBT, includes a semiconductor body on which at least two mutually spaced apart electrodes are provided,...
US-6,803,301 Fuse configuration with modified capacitor border layout for a semiconductor storage device
A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first...
US-6,803,156 Electrostatic damage (ESD) protected photomask
A photomask (8) protected against electrostatic damage and a method of manufacturing such a photomask is disclosed. The photomask (8) comprises a transparent...
US-6,802,712 Heating system, method for heating a deposition or oxidation reactor, and reactor including the heating system
A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for...
US-6,801,757 Circuit configuration for matching an amplifier to a radio-frequency line, and use of the circuit configuration
A circuit for matching an amplifier to a radio-frequency line is described. In order to minimize the number of components required for matching the amplifier to...
US-6,801,471 Fuse concept and method of operation
It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on...
US-6,801,314 Alignment system and method using bright spot and box structure
There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is...
US-6,801,087 Integrated circuit with an analog amplifier
An integrated circuit includes an analog amplifier connected to a terminal pad and has a Miller compensation of a section of the analog amplifier. The Miller...
US-6,801,024 Method of frequency limitation and overload detection in a voltage regulator
A regulated output voltage and an output current are generated by using a switching device for providing the output current and controlling the switching device...
US-6,800,926 Tracking circuit
Tracking circuit for tracking the voltage potential of an insulation well for the insulation of an integrated component (1) embedded in the insulation well, the...
US-6,800,925 Integrated circuit configuration having a structure for reducing a minority charge carrier current
An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and...
US-6,800,898 Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench...
The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first...
US-6,800,893 Semiconductor circuit configuration and associated fabrication method
The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of...
US-6,800,890 Memory architecture with series grouped by cells
An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel....
US-6,800,817 Semiconductor component for connection to a test system
The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor...
US-6,800,407 Method for experimentally verifying imaging errors in photomasks
The method enables determining imaging errors of photomasks for the lithographic structuring of semiconductors. A latent image of the mask is first produced in a...
US-6,799,290 Data path calibration and testing mode using a data bus for semiconductor memories
A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device...
US-6,798,706 Integrated circuit with temperature sensor and method for heating the circuit
A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least...
US-6,798,689 Integrated memory with a configuration of non-volatile memory cells and method for fabricating and for...
An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive...
US-6,798,303 Clock signal generating device
A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished...
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