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Patent # Description
US-6,774,825 Modulation coding based on an ECC interleave structure
A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks...
US-6,774,738 Trimming method for a transceiver using two-point modulation
In a method for amplitude trimming in transceivers having a PLL circuit operating on the two-point modulation principle, the amplitude of an analog modulation...
US-6,774,691 High resolution interleaved delay chain
An improved delay chain for use in a delay locked loop which provides smooth phase adjustment and high resolution. In a delay chain having a series of cascaded...
US-6,774,688 Circuit for synchronizing signals during the exchange of information between circuits
A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is...
US-6,774,682 Circuit configuration for driving a semiconductor switching element and method for same
A circuit configuration for driving a semiconductor switching element includes an output terminal for the connection of a semiconductor switching element, a...
US-6,774,649 Test system for conducting a function test of a semiconductor element on a wafer, and operating method
A test system for conducting a function test of a semiconductor element on a wafer and a method for conducting the test includes a voltage source providing a...
US-6,774,483 Semiconductor assembly with a semiconductor module
A semiconductor assembly includes a module holder and a semiconductor module, which has a board substrate with conductor tracks and one or more unpackaged...
US-6,774,479 Electronic device having a semiconductor chip on a semiconductor chip connection plate and a method for...
The invention relates to an electronic device having a semiconductor chip and a leadframe. The leadframe has a flat conductor frame. A semiconductor chip...
US-6,774,456 Configuration of fuses in semiconductor structures with Cu metallization
A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the...
US-6,774,425 Metal-insulator-metal capacitor and a method for producing same
A capacitor stack in a layer structure of an integrated component has the same layer sequence as an adjacent interconnect, with the exception of a dielectric...
US-6,774,005 Method for fabricating a metal carbide layer and method for fabricating a trench capacitor containing a metal...
At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal...
US-6,773,986 Method for fabricating a semiconductor memory device
To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the...
US-6,773,983 Memory cell arrangement and method for its fabrication
The present invention relates to a memory cell arrangement and a fabrication method for this memory cell arrangement. In this case, the memory cells (15a, 15b,...
US-6,773,956 Method for contact-connecting a semiconductor component
A solder metal made of a eutectic or stoichiometric composition including at least two metallic or semiconducting elements is applied to a contact (of the...
US-6,773,934 Method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer
A method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer, each of which having a plurality of interconnected...
US-6,773,854 Method of producing a perforated mask for particle radiation
A method for producing a perforated mask for particle radiation includes calculating values of an elasticity of adjacent cells of a mask with respect to...
US-6,773,169 Method for coupling a surface-oriented opto-electronic element with an optical fiber and opto-electronic...
A method for coupling a surface-oriented opto-electronic element, particularly, a VCSEL laser diode, an LED, or a photodiode, with an optical fiber and an...
US-6,771,937 Frequency-stabilized transmitting/receiving configuration
A circuit configuration has a radio-frequency section with a receiving mixing stage, and has a signal processing circuit with an A/D converter, a digital filter...
US-6,771,711 Digital GMSK filter
A digital GMSK filter for use for frequency modulation of a carrier signal in a GMSK transmission system is described. The GMSK filter uses a large number of...
US-6,771,701 Adaptive filter divergence control in echo cancelers by means of amplitude distribution evaluation with...
A configurable adaptive filter that is used for echo cancellation is disclosed, which includes a method of detecting a voice or no-voice signal. The presence of...
US-6,771,527 Integrated DRAM memory component
An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of...
US-6,771,442 Off-track interference emulator
An apparatus and method for adding errors to magnetic data and then detecting the errors is revealed. The method includes providing a magnetic recording channel,...
US-6,770,953 Bipolar transistor
A bipolar transistor is provided in which the product of base-collector capacitance and collector resistance can be reduced through a layout optimization, which...
US-6,770,928 Semiconductor memory with vertical selection transistor
A semiconductor memory having memory cells, each memory cell includes a selection transistor and a trench capacitor. The selection transistor is formed in the...
US-6,770,917 High-voltage diode
A high-voltage diode and a method for producing the high-voltage diode involve only three masking steps. Only three masking steps are required due to the use of...
US-6,770,530 Method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a...
The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A...
US-6,770,526 Silicon nitride island formation for increased capacitance
A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor...
US-6,770,423 Negative resist process with simultaneous development and silylation
The invention relates to a process for producing amplified negative resist structures in which, following exposure and contrasting of the resist in a developing...
US-6,769,065 Access authorization device for controlling access requested by an OCDS module
A program-controlled unit with an on-chip debug support (OCDS) module and a method for debugging a program-controlled unit fitted with the OCDS module by using...
US-6,769,035 Same single board computer system operable as a system master and a bus target
A same single board computer system that is operable as a system master and a bus target and methods of operating the same are described. In one system, a...
US-6,768,826 Delivering data optically to an integrated circuit
A system includes a multi-sided module having a cavity housing a substrate and n photoreceivers located on a side of the substrate and adapted to receive a beam...
US-6,768,770 Transceiver with bidirectional internal interface lines
A transceiver has bidirectional internal interface lines which can be connected to a baseband circuit. The transceiver is switchable by the baseband circuit...
US-6,768,695 Circuit configuration for driving a programmable link
A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a...
US-6,768,693 Integrated dynamic memory with control circuit for controlling a refresh mode of memory cells, and method for...
An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A...
US-6,768,686 Read/write amplifier for a DRAM memory cell, and DRAM memory
A description is given of a DRAM memory (10) having a number of DRAM memory cells (15) which each form one or more memory cell arrays (11). Each memory cell (15)...
US-6,768,668 Converting volatile memory to non-volatile memory
The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile...
US-6,768,667 Semiconductor memory device
A DRAM memory cell having an isolation transistor formed from a bipolar transistor.
US-6,768,191 Electronic component with stacked electronic elements
An electronic component includes stacked electronic elements with external contacts. The external contacts are connected to contact terminal pads of an...
US-6,768,169 Transistor having compensation zones enabling a low on-resistance and a high reverse voltage
A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is...
US-6,768,166 Vertical transistor, memory arrangement and method for fabricating a vertical transistor
A vertical transistor (100) has a source region (103), a drain region (109), a gate region (108), and a channel region (104) between the source region (103) and...
US-6,768,155 Circuit with buried strap including liner
Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such...
US-6,768,150 Magnetic memory
A magnetic memory cell is disclosed. The memory cell includes first conductor and second conductors coupled to first and second electrodes of a magnetic element....
US-6,768,139 Transistor configuration for a bandgap circuit
A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type...
US-6,767,781 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask
A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed....
US-6,767,682 Method for producing quadratic contact holes utilizing side lobe formation
An array of small square contact holes, on the order of magnitude of the exposing light wavelength, are formed by selecting the partial coherence and numerical...
US-6,767,674 Method for obtaining elliptical and rounded shapes using beam shaping
A method of fabricating a mask (316) for patterning a semiconductor wafer. The mask (316) includes elliptical (340) or rounded features formed using an...
US-6,767,581 Process for the deposition of thin layers by chemical vapor deposition
A process for the deposition of thin layers by chemical vapor deposition includes adding an effective amount of nitroxyl radicals of the formula ##STR1## to a...
US-6,767,170 Wafer handling system and wafer handling method
A wafer holder has a set of minimum contact wafer support members predefining support member contacting portions on a planar wafer surface of a wafer. The wafer...
US-6,765,951 Method for estimating the channel impulse response of a mobile radio channel
A method for estimating a channel impulse response of a mobile radio channel is described. The mobile radio channel is accessed over a wide bandwidth by a code...
US-6,765,848 Focus and tracking repeatable runout compensator
A repeatable runout compensator that allows a transducer of a servo system in a storage device employing rotating media to follow the eccentricity on the media...
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