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Patent # Description
US-6,762,635 Clock generator, particularly for USB devices
In accordance with the USB specifications, an accuracy of 0.25% is required for the data transmission rate. To generate a clock signal that allows this accuracy,...
US-6,762,630 Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated...
An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing...
US-6,762,611 Test configuration and test method for testing a plurality of integrated circuits in parallel
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test...
US-6,762,589 Circuit for charging rechargeable batteries having a combined charging and overvoltage protection circuit
A rechargeable battery unit, which is intended for supplying a voltage to an electrical appliance, is charged by an external charging voltage by a charging...
US-6,762,455 Semiconductor component for high reverse voltages in conjunction with a low on resistance and method for...
A semiconductor component includes a semiconductor body of a first conductivity type which accommodates a space charge region. Semiconductor regions of a second...
US-6,762,447 Field-shield-trench isolation for gigabit DRAMs
A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical...
US-6,762,443 Vertical transistor and transistor fabrication method
In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the...
US-6,762,440 Semiconductor component and corresponding test method
A semiconductor component having a first main terminal, a second main terminal, a gate terminal for controlling the current between the main terminals is...
US-6,762,066 Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure
A method produces a semiconductor structure on a substrate. Then, a protective layer is applied to the semiconductor structure. To fabricate a further...
US-6,762,064 Process for fabrication of a ferrocapacitor
A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric...
US-6,761,620 Finishing pad design for multidirectional use
A polishing pad (for example, polishing pad 305) for use in planarization of a semiconductor wafer (for example, semiconductor wafer 420), the polishing pad 305...
US-6,761,488 Holding device for holding at least one optical plug
The invention relates to a holding device for holding at least one optical plug that can be coupled with a coupling partner in an optical coupling system....
US-6,760,992 Electronic security device for a firearm and associated electronically coded ammunition
An apparatus for releasing a safety device of a firearm with a trigger for actuating the apparatus, wherein the safety device is capable of blocking the...
US-6,760,261 DQS postamble noise suppression by forcing a minimum pulse length
A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data...
US-6,760,260 Semiconductor memory apparatus
A semiconductor memory apparatus includes a memory cell array having a multiplicity of data lines and a multiplicity of local amplifiers, each of the local...
US-6,760,252 Floating gate memory cell, method for fabricating it, and semiconductor memory device
For particularly flexible and space-saving information storage, in the case of a floating gate memory cell and a corresponding semiconductor memory device, the...
US-6,760,248 Voltage regulator with distributed output transistor
A memory device and method of manufacturing thereof having a voltage regulator with distributed output transistor. A novel approach for the bitline high voltage...
US-6,759,894 Method and circuit for controlling fuse blow
A method and circuit for controlling fuse blow including sending signals to a plurality of fuse latches, sending fuse select signals to a blow control circuit to...
US-6,759,890 Integrated semiconductor module with a bridgeable input low-pass filter
An integrated semiconductor module having at least one terminal for connection to a data bus and having at least one low-pass filter that is connected downstream...
US-6,759,879 Storage circuit
A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first...
US-6,759,874 Electronic circuit with a driver circuit
An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward...
US-6,759,854 Test apparatus for testing devices under test and method for transmitting a test signal
A test apparatus comprises an input for receiving a test signal from a test signal source, wherein a signal line with a predefined characteristic wave impedance...
US-6,759,323 Method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled...
A method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way. On a semiconductor structure, in...
US-6,759,292 Method for fabricating a trench capacitor
A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent...
US-6,759,184 Amplification of resist structures of fluorinated resist polymers by structural growth of the structures by...
A process for the post-exposure amplification of resist structures uses amplification of resist structures of fluorinated resist polymers by structural growth of...
US-6,758,223 Plasma RIE polymer removal
A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising: supplying a...
US-6,757,834 Method and arrangement for minimizing power dissipation in a line driver
To minimize power dissipation in a line driver (3) in a central office (CO) for driving a DSL connection to a network terminal (NT) with a predetermined maximum...
US-6,757,763 Universal serial bus interfacing using FIFO buffers
An improved Universal Serial Bus interface employing FIFO buffers (300, 800) for interfacing to an application bus and a microprocessor bus, in particular, an...
US-6,757,460 Electro-optical module for transmitting and/or receiving optical signals on at least two optical data channels
The invention relates to an electro-optical module for transmitting and/or receiving optical signals on at least two optical data channels which are carried in...
US-6,757,204 Circuit device having a fuse
A semiconductor memory device includes a plurality of integrated circuit modules each having a plurality of module elements and at least one adjustable module...
US-6,757,187 Integrated magnetoresistive semiconductor memory and fabrication method for the memory
An integrated magnetoresistive semiconductor memory in which each memory cell contains a switching transistor or a diode in the form of an activatable isolating...
US-6,757,183 Method for starting up a switched-mode power supply, and switched-mode power supply having a starting circuit
To start a switching power supply in an energy saving manner, the method and device according to the invention transmits the energy that is collected by the...
US-6,757,171 Device for fixing a heat distribution covering on a printed circuit board with heat distribution covering
A device for fixing a heat distribution covering on a printed circuit board includes at least one fixing foot disposed on a placement area next to a plurality of...
US-6,756,927 Sigma-delta programming device for a PLL frequency synthesizer, configuration using the sigma-delta programming...
A sigma-delta programmer is supplied with a data word having a word length of N bits. The most significant L bits of the data word represent the places before...
US-6,756,920 Coding device, decoding device, method for coding, and method for decoding
A coding device is able to convert the data that is to be coded to data having different characteristics. The decoding device is able to decode differently coded...
US-6,756,877 Shunt resistor configuration
The present invention relates to a configuration having a first shunt resistor and at least one second shunt resistor connected in parallel with the first shunt...
US-6,756,851 Transimpedance amplifier
Transimpedance amplifier having an input stage (1) to which an input current to be amplified is fed and an output stage (2) which outputs an output voltage...
US-6,756,792 Apparatus for measuring parasitic capacitances on an integrated circuit
The novel apparatus permits precise measurements of parasitic capacitances. The apparatus has a test structure and a reference structure, each with two conductor...
US-6,756,787 Integrated circuit having a current measuring unit
The invention relates to an integrated circuit having a circuit and a current measuring unit for measuring the current through the functional circuit. The...
US-6,756,699 Device and method for calibrating the pulse duration of a signal source
An apparatus for calibrating the pulse duration of an output signal of a signal source may be used, in particular, for measuring and setting a duty cycle of a...
US-6,756,655 Fuse for a semiconductor configuration and method for its production
A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the...
US-6,756,626 Trench capacitor having an insulation collar
A trench capacitor has a bottle-shaped trench in a semiconductor substrate. The bottle-shaped trench has a wider lower region and a narrower upper region. An...
US-6,756,540 Self-adhering chip
An integrated circuit (chip) with attachment elements for attaching of the chip on a carrier, the attachment elements being designed in a way such that they can...
US-6,756,314 Method for etching a hard mask layer and a metal layer
An improved insitu hard mask open strategy is performed before carrying out a metal etching process. The method for opening the hard mask made of SiO.sub.2,...
US-6,756,254 Integrated circuit having an antifuse and a method of manufacture
An integrated circuit is formed by a method having the steps of providing a circuit substrate with a first metallized region, providing a first insulation layer...
US-6,756,164 Exposure mask with repaired dummy structure and method of repairing an exposure mask
An exposure mask has a phase mask and a phase-shifting dummy structure. The exposure mask can be repaired with regard to defects in the dummy structure. For that...
US-6,756,162 Stencil mask for high- and ultrahigh-energy implantation
A stencil mask for high- and ultrahigh-energy implantation of semiconductor wafers has a substrate with implantation openings through which the implantation...
US-6,754,869 Method and device for testing set-up time and hold time of signals of a circuit with clocked data transfer
For testing, a reference clock signal is applied to a first delay path having a fixed delay and a second delay path having a variable delay. The delay paths are...
US-6,754,116 Test of a semiconductor memory having a plurality of memory banks
A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously...
US-6,754,113 Topography correction for testing of redundant array elements
A data topography correction circuit for a semiconductor memory device and method for testing the device is provided. The data topography correction circuit...
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