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Patent # Description
US-6,794,259 Method for fabricating self-aligning mask layers
A method for fabricating a self-aligning mask layer includes the steps of forming a surface to be masked in a carrier substrate, the surface having different...
US-6,794,249 Method for fabricating a memory cell
An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the...
US-6,794,242 Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing...
A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically...
US-6,794,209 Method for the in-situ fabrication of DFB lasers
The invention relates to a method for fabricating a structure in a semiconductor material. At least one etching step is carried out in-situ in an epitaxy...
US-6,794,095 Method of fabricating a microstructure and photolithography trimming mask
A photolithographic fabrication method for a microstructure on a substrate, in particular interconnects of a DRAM (dynamic random access memory), includes a...
US-6,792,036 Method for estimating channel impulse responses of a mobile radio channel
A method is described for estimating channel impulse responses of a mobile radio channel with a broad bandwidth by a code division multiplexing method, and with...
US-6,791,871 MRAM configuration
An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving...
US-6,791,420 Phase locked loop for recovering a clock signal from a data signal
A phase locked loop for recovering a clock signal from a data signal including a delay locked loop with a nonlinear digital phase detector. The delay locked loop...
US-6,791,411 Power amplifier and a method for operating a power amplifier
According to the invention, the high-frequency power amplifier is characterised in that the power transistor is switched in such a way that said transistor is...
US-6,791,358 Circuit configuration with signal lines for serially transmitting a plurality of bit groups
A circuit configuration has a transmitter unit connected to a first signal line and a receiver unit connected to a second signal line and is coupled to the...
US-6,791,357 Bus signal hold cell, bus system, and method
The invention relates to an integrated bus signal hold cell that is coupled with a bus line via a common input/output, and that has at least two inverters for...
US-6,791,349 Electrical component with a contact and method for forming a contact on a semiconductor material
An electrical component contains a pad formed of an electrically conductive material. The pad serves for the application of a contact element and is complemented...
US-6,791,303 Circuit configuration for voltage stabilization
A voltage stabilization circuit is configured between two signal lines. Each of the signal lines carries a signal, and an interference signal is superimposed on...
US-6,791,183 Power semiconductor module and cooling element for holding the power semiconductor module
A power semiconductor module and a cooling element for holding the power semiconductor module are described. The power semiconductor module has a housing that...
US-6,791,074 Light curtain system for establishing a protective light curtain, tool and system for processing objects and...
A light curtain system is provided for establishing a protective light curtain for a tool in a system for processing objects such as wafers, and is particularly...
US-6,790,737 Method for fabricating thin metal layers from the liquid phase
A method for producing metal layers on surfaces of semiconductor substrates includes the step of providing a semiconductor substrate having a surface. In this...
US-6,790,726 Method for producing an integrated semiconductor memory configuration
A method for producing an integrated semiconductor memory configuration includes forming two capacitor modules for each selection transistor from the front and...
US-6,790,676 Method for producing a ferroelectric layer
A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the...
US-6,789,958 Release mechanism for pluggable fiber optic transceiver
A release mechanism for manually securing a pluggable fiber optic transceiver to a cage mounted on a host circuit board. The release mechanism includes a...
US-6,789,939 Temperature sensor and method for operating a temperature sensor
The invention relates to a temperature sensor having a first FET transistor circuit and a second FET transistor circuit and also to a method for operating a...
US-6,789,150 Integrated circuit having arbitrated switching between busses
An integrated circuit (1) includes a processing device (2), a program interface (4, 5) coupled to the processing device (2), a data interface (6, 7) coupled to...
US-6,788,850 Configuration for multiplexing and/or demultiplexing the signals of at least two optical wavelength channels
A configuration for multiplexing and/or demultiplexing the signals of at least two optical wavelength channels, is described. Provided in this case is a grating...
US-6,788,784 Circuit arrangement for signaling in telecommunications networks
A circuit arrangement for signaling in telecommunications networks has a first connection and a second connection for a first and a second conductor,...
US-6,788,606 Method and apparatus for refreshing memory cells
In a memory element with a first number of memory cells having a first retention time for holding a content of the memory cells and a second number of memory...
US-6,788,548 Adapter apparatus for memory modules
An adapter apparatus for receiving memory modules, each of which has a plurality of data terminals and a plurality of control terminals, comprises first data...
US-6,788,485 Synchronous timing for interpolated timing recovery
A phase error estimate value between an actual interpolated sample time and an ideal interpolated sample time of an analog signal is selected by circuitry based...
US-6,788,482 Method and apparatus for Viterbi detector state metric re-normalization
A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector (138) having a predetermined number...
US-6,788,235 A/D converter having signaling and requesting capability
The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of...
US-6,788,228 Addressing device for selecting regular and redundant elements
An addressing device selects an element from a set of N.ltoreq.2.sup.K regular elements or alternatively from a set of R<N redundant elements in dependence on...
US-6,788,223 High rate coding for media noise
An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b.sub.1, b.sub.2, b.sub.3 . . ....
US-6,788,145 Circuit configuration for producing exponential predistortion for a variable amplifier
A circuit is specified for producing exponential predistortion for a variable amplifier that contains two parallel-connected, controlled current paths, each...
US-6,788,129 Integrated circuit having a programmable element and method of operating the circuit
An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the...
US-6,788,087 Integrated circuit having a test circuit, and method of decoupling a test circuit in an integrated circuit
The integrated circuit has a test circuit, which is connected to an input terminal of the integrated circuit via a line connection. An isolating device is...
US-6,787,843 Nonvolatile semiconductor memory cell and associated semiconductor circuit configuration and method for the...
A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active...
US-6,787,832 Semiconductor memory cell and semiconductor memory device
A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region...
US-6,787,831 Barrier stack with improved barrier properties
An barrier stack for inhibiting diffusion of atoms or molecules, such as O.sub.2 is disclosed. The barrier slack includes first and second barrier layers formed...
US-6,787,799 Device and method for detecting a reliability of integrated semiconductor components at high temperatures
The invention relates to a device and a method for detecting the reliability of integrated semiconductor components. The device includes a carrier substrate for...
US-6,787,431 Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers
A method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers. In the method, an alignment mark region surrounded by...
US-6,787,244 Adhesively bonded chip-and wafer stacks
The present invention describes the use of poly-o-hydroxy amides (PHAs) for adhesively bonding articles or materials, especially components used in the...
US-6,787,242 Methods of using adhesion enhancing layers and microelectronic integrated modules including adhesion enhancing...
Adhesion promoters for polymer coatings on metals are articulated into at least two head groups connected by a hydrocarbon spacer group. One head group reacts...
US-6,787,186 Method of controlled chemical vapor deposition of a metal oxide ceramic layer
A method of forming a metal oxide ceramic layer is provided, in which a gaseous flow of a vaporized solution of a precursor organo metal compound in a volatile...
US-6,786,335 Pyrolysis plant for refuse and method for screening solid residues
A pyrolysis plant for refuse and a method for screening solid residues provide a sure and trouble-free sieving of a solid material using a sieving device having...
US-6,785,476 Transmission configuration
A transmission configuration includes a plurality of individual lasers which are included in a two-dimensional laser array and emit radiation elements with...
US-6,785,348 Demodulator and method for demodulating CPFSK-modulated signals using a linear approximation of the CPFSK signal
In a method for demodulating a CPFSK-modulated signal, the n-1-th substitute symbol a.sub.n-1 which occurs in the linear approximation of the CPFSK is estimated...
US-6,785,284 Interleavement for transport of frames and cells
A DMA system includes a plurality of transmit-receive pairs (102, 104) for communicating on a bus. A DMA controller (108) supervises bus handling. The DMA...
US-6,785,170 Data memory with short memory access time
A data memory including a main data memory having a plurality of data memory units, a redundancy data memory that includes a plurality of redundancy data memory...
US-6,785,119 Ferroelectric capacitor and process for its manufacture
Forming a capacitor, by (a) forming a matrix of ferroelectric capacitor elements on a substrate, (b) forming a CAP layer over the ferroelectric capacitor...
US-6,784,929 Universal two dimensional (frame and line) timing generator
A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106,...
US-6,784,691 Integrated circuit having a connection pad for stipulating one of a plurality of organization forms, and method...
An integrated circuit can be operated in at least three different organization forms that can be set externally. A connection pad receives an external signal for...
US-6,784,683 Circuit configuration for selectively transmitting information items from a measuring device to chips on a...
The circuit configuration allows selective transmission of information items to a chip of a wafer during chip fabrication, and an apparatus having a needle card....
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