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Linked list DMA descriptor architecture
A linked list DMA descriptor includes an indication of a number of data pointers contained in a subsequent DMA descriptor. The number of data pointers contained...
Graphical user interface for testing integrated circuits
A system that includes a graphical user interface (GUI) connected to an input/output device of a computer system and one or more test instruments producing a set...
Asynchronous data reception circuit of a serial data stream
Data reception circuit for receiving a serial input data stream, where the data reception circuit has a data stream separation circuit (4) for separating the...
Method and apparatus for generating reliability information for channel
decoding in a radio receiver
An equalizer of a radio receiver for generating reliability information (q) that specifies probabilities of a received data symbol (z) being based on a...
A method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines...
MRAM semiconductor memory configuration with redundant cell arrays
The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell...
Method for operating a semiconductor memory and semiconductor memory
An additional test mode is introduced in a semiconductor memory. A multiplicity of word lines are simultaneously activated by a word line decoder in the test...
Configuration for operating an optical transmission or reception module at
high data rates of up to 10 Gbit/s
The invention relates to an arrangement for operating an optical transmission or reception module at high data rates of up to 10 Gbit/s, having a TO package with...
Electronic output stage
An electronic output module, especially an electronic output module for CMOS-LVDS levels (LVDS-low voltage differential signalling), is suitable for analogue and...
Method and device for generating a reference voltage
A method and a device generate a reference voltage for discriminating between the logic states of a data signal received at a receiving end. A transmitting...
Zero static power programmable fuse cell for integrated circuits
A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell can be operated in programmable...
Programming transistor in breakdown mode with current compliance
A transistor (such as a MOSFET) is operated in its breakdown region, as opposed to its saturation region, to program an electric fuse. With the programming...
Circuit for testing an integrated circuit
A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal...
Semiconductor device and converter device with an integrated capacitor
In order to keep the mounting outlay for shielding measures as low as possible, a semiconductor device having a semiconductor component in a housing element is...
Printed circuit board for semiconductor memory device
In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of...
Optoelectronic component with thermally conductive auxiliary carrier
The invention relates to an optoelectronic component with a light emitting or light receiving element (1) and a system carrier (9) supporting the element (1)....
Trench capacitor and method for fabricating the same
A trench capacitor for use in a semiconductor memory cell is formed in a substrate and includes a trench having an upper region and a lower region. An insulation...
Electrical arrangement and method for producing an electrical arrangement
The invention relates to an electrical arrangement having a mount device with at least one conductor track, having an electrical component that is mounted on the...
Design of lithography alignment and overlay measurement marks on CMP
finished damascene surface
A method for producing a semiconductor device having an alignment mark, the method comprising forming a first dielectric layer within which a trench having...
Reduction of negative bias temperature instability in narrow width PMOS
using F2 implantation
In a process of fabricating a narrow channel width PMOSFET device, the improvement of affecting reduction of negative bias temperature instability by use of...
Method for controlling the quality of a lithographic structuring step
After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured...
Method for trench etching
The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching,...
Method for testing the refresh device of an information memory
A method for testing the refresh device of an information memory contains the following: a refresh selector for selecting memory cells to be refreshed; a sensor...
Optical transmission device
The transmission device comprises at least one laser transmitter (1) which emits light (2) as a function of binary data signals (24) which are to be transmitted,...
Portable data carrier
A portable data carrier includes a card-shaped body having a recess for receiving a chip module. The chip module includes at least one semiconductor chip on a...
Bubble handling A/D converter calibration
An A/D converter includes a calibration apparatus handling occurrences of thermometer code bubbles in an A/D sub-converter in at least one A/D converter stage....
Delay lock loop having an edge detector and fixed delay
A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit...
Arrangement and method for adjustment of the slope times for one or more
drivers and a driver circuit
The invention relates to an arrangement (10) and a method for adjusting the slope times of one or more drivers (90) in such a way that the adjustment is...
Method of inferring the existence of light by means of a measurement of the
electrical characteristics of a...
A method of inferring the existence of light by means of a measurement of the electrical characteristics of a nanotube bound to a dye first of all involves...
Method and magazine device for testing semiconductor devices
A method and device allow testing functionally identical semiconductor devices on a programmable testing device. The semiconductor devices are placed in magazine...
Multiple ground signal path LDMOS power package
A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a...
Magnetoresistive memory cell with polarity-dependent resistance
A magnetoresistive tunnel element includes first and second electrodes and a tunnel barrier disposed between the two electrodes, the tunnel barrier having at...
MOSFET source, drain and gate regions in a trench between a semiconductor
pillar and filling insulation
In a metal oxide semiconductor (MOS) field effect transistor configuration, a source, a drain and a gate are embedded between a semiconductor pillar that extends...
Method for fabricating an insulation collar in a trench capacitor
A trench capacitor is formed with an insulation collar. After the formation of the trench, firstly an insulating layer is deposited, from which layer the...
Electronic component with isolation barriers between the terminal pins
An electronic component has a housing and at least two terminal pins protruding out from a first side face of the housing. The housing has an isolation barrier...
Method and apparatus for testing an SDRAM memory used as the main memory in
a personal computer
A method and an apparatus for testing an SDRAM are described. The SDRAM is used as a main memory in the PC, and an additional circuit configuration is...
Integrated magnetoresistive semiconductor memory configuration
An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier,...
An optoelectronic module has a laser diode configured on a substrate. The laser diode is drivable using an electronic drive device. At least one electrode of the...
Modulation coding based on an ECC interleave structure
A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks...
Trimming method for a transceiver using two-point modulation
In a method for amplitude trimming in transceivers having a PLL circuit operating on the two-point modulation principle, the amplitude of an analog modulation...
High resolution interleaved delay chain
An improved delay chain for use in a delay locked loop which provides smooth phase adjustment and high resolution. In a delay chain having a series of cascaded...
Circuit for synchronizing signals during the exchange of information
A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is...
Circuit configuration for driving a semiconductor switching element and
method for same
A circuit configuration for driving a semiconductor switching element includes an output terminal for the connection of a semiconductor switching element, a...
Test system for conducting a function test of a semiconductor element on a
wafer, and operating method
A test system for conducting a function test of a semiconductor element on a wafer and a method for conducting the test includes a voltage source providing a...
Semiconductor assembly with a semiconductor module
A semiconductor assembly includes a module holder and a semiconductor module, which has a board substrate with conductor tracks and one or more unpackaged...
Electronic device having a semiconductor chip on a semiconductor chip
connection plate and a method for...
The invention relates to an electronic device having a semiconductor chip and a leadframe. The leadframe has a flat conductor frame. A semiconductor chip...
Configuration of fuses in semiconductor structures with Cu metallization
A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the...
Metal-insulator-metal capacitor and a method for producing same
A capacitor stack in a layer structure of an integrated component has the same layer sequence as an adjacent interconnect, with the exception of a dielectric...
Method for fabricating a metal carbide layer and method for fabricating a
trench capacitor containing a metal...
At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal...
Method for fabricating a semiconductor memory device
To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the...