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Patent # Description
US-6,791,303 Circuit configuration for voltage stabilization
A voltage stabilization circuit is configured between two signal lines. Each of the signal lines carries a signal, and an interference signal is superimposed on...
US-6,791,183 Power semiconductor module and cooling element for holding the power semiconductor module
A power semiconductor module and a cooling element for holding the power semiconductor module are described. The power semiconductor module has a housing that...
US-6,791,074 Light curtain system for establishing a protective light curtain, tool and system for processing objects and...
A light curtain system is provided for establishing a protective light curtain for a tool in a system for processing objects such as wafers, and is particularly...
US-6,790,737 Method for fabricating thin metal layers from the liquid phase
A method for producing metal layers on surfaces of semiconductor substrates includes the step of providing a semiconductor substrate having a surface. In this...
US-6,790,726 Method for producing an integrated semiconductor memory configuration
A method for producing an integrated semiconductor memory configuration includes forming two capacitor modules for each selection transistor from the front and...
US-6,790,676 Method for producing a ferroelectric layer
A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the...
US-6,789,958 Release mechanism for pluggable fiber optic transceiver
A release mechanism for manually securing a pluggable fiber optic transceiver to a cage mounted on a host circuit board. The release mechanism includes a...
US-6,789,939 Temperature sensor and method for operating a temperature sensor
The invention relates to a temperature sensor having a first FET transistor circuit and a second FET transistor circuit and also to a method for operating a...
US-6,789,150 Integrated circuit having arbitrated switching between busses
An integrated circuit (1) includes a processing device (2), a program interface (4, 5) coupled to the processing device (2), a data interface (6, 7) coupled to...
US-6,788,850 Configuration for multiplexing and/or demultiplexing the signals of at least two optical wavelength channels
A configuration for multiplexing and/or demultiplexing the signals of at least two optical wavelength channels, is described. Provided in this case is a grating...
US-6,788,784 Circuit arrangement for signaling in telecommunications networks
A circuit arrangement for signaling in telecommunications networks has a first connection and a second connection for a first and a second conductor,...
US-6,788,606 Method and apparatus for refreshing memory cells
In a memory element with a first number of memory cells having a first retention time for holding a content of the memory cells and a second number of memory...
US-6,788,548 Adapter apparatus for memory modules
An adapter apparatus for receiving memory modules, each of which has a plurality of data terminals and a plurality of control terminals, comprises first data...
US-6,788,485 Synchronous timing for interpolated timing recovery
A phase error estimate value between an actual interpolated sample time and an ideal interpolated sample time of an analog signal is selected by circuitry based...
US-6,788,482 Method and apparatus for Viterbi detector state metric re-normalization
A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector (138) having a predetermined number...
US-6,788,235 A/D converter having signaling and requesting capability
The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of...
US-6,788,228 Addressing device for selecting regular and redundant elements
An addressing device selects an element from a set of N.ltoreq.2.sup.K regular elements or alternatively from a set of R<N redundant elements in dependence on...
US-6,788,223 High rate coding for media noise
An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b.sub.1, b.sub.2, b.sub.3 . . ....
US-6,788,145 Circuit configuration for producing exponential predistortion for a variable amplifier
A circuit is specified for producing exponential predistortion for a variable amplifier that contains two parallel-connected, controlled current paths, each...
US-6,788,129 Integrated circuit having a programmable element and method of operating the circuit
An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the...
US-6,788,087 Integrated circuit having a test circuit, and method of decoupling a test circuit in an integrated circuit
The integrated circuit has a test circuit, which is connected to an input terminal of the integrated circuit via a line connection. An isolating device is...
US-6,787,843 Nonvolatile semiconductor memory cell and associated semiconductor circuit configuration and method for the...
A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active...
US-6,787,832 Semiconductor memory cell and semiconductor memory device
A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region...
US-6,787,831 Barrier stack with improved barrier properties
An barrier stack for inhibiting diffusion of atoms or molecules, such as O.sub.2 is disclosed. The barrier slack includes first and second barrier layers formed...
US-6,787,799 Device and method for detecting a reliability of integrated semiconductor components at high temperatures
The invention relates to a device and a method for detecting the reliability of integrated semiconductor components. The device includes a carrier substrate for...
US-6,787,431 Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers
A method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers. In the method, an alignment mark region surrounded by...
US-6,787,244 Adhesively bonded chip-and wafer stacks
The present invention describes the use of poly-o-hydroxy amides (PHAs) for adhesively bonding articles or materials, especially components used in the...
US-6,787,242 Methods of using adhesion enhancing layers and microelectronic integrated modules including adhesion enhancing...
Adhesion promoters for polymer coatings on metals are articulated into at least two head groups connected by a hydrocarbon spacer group. One head group reacts...
US-6,787,186 Method of controlled chemical vapor deposition of a metal oxide ceramic layer
A method of forming a metal oxide ceramic layer is provided, in which a gaseous flow of a vaporized solution of a precursor organo metal compound in a volatile...
US-6,786,335 Pyrolysis plant for refuse and method for screening solid residues
A pyrolysis plant for refuse and a method for screening solid residues provide a sure and trouble-free sieving of a solid material using a sieving device having...
US-6,785,476 Transmission configuration
A transmission configuration includes a plurality of individual lasers which are included in a two-dimensional laser array and emit radiation elements with...
US-6,785,348 Demodulator and method for demodulating CPFSK-modulated signals using a linear approximation of the CPFSK signal
In a method for demodulating a CPFSK-modulated signal, the n-1-th substitute symbol a.sub.n-1 which occurs in the linear approximation of the CPFSK is estimated...
US-6,785,284 Interleavement for transport of frames and cells
A DMA system includes a plurality of transmit-receive pairs (102, 104) for communicating on a bus. A DMA controller (108) supervises bus handling. The DMA...
US-6,785,170 Data memory with short memory access time
A data memory including a main data memory having a plurality of data memory units, a redundancy data memory that includes a plurality of redundancy data memory...
US-6,785,119 Ferroelectric capacitor and process for its manufacture
Forming a capacitor, by (a) forming a matrix of ferroelectric capacitor elements on a substrate, (b) forming a CAP layer over the ferroelectric capacitor...
US-6,784,929 Universal two dimensional (frame and line) timing generator
A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106,...
US-6,784,691 Integrated circuit having a connection pad for stipulating one of a plurality of organization forms, and method...
An integrated circuit can be operated in at least three different organization forms that can be set externally. A connection pad receives an external signal for...
US-6,784,683 Circuit configuration for selectively transmitting information items from a measuring device to chips on a...
The circuit configuration allows selective transmission of information items to a chip of a wafer during chip fabrication, and an apparatus having a needle card....
US-6,784,678 Test apparatus for semiconductor circuit and method of testing semiconductor circuits
A wafer test apparatus for bringing the contact areas of the integrated circuits to be tested into electrical connection with the test contacts as uniformly as...
US-6,784,553 Semiconductor device with self-aligned contact and method for manufacturing the device
A semiconductor device and a method for manufacturing the semiconductor device with a self-aligned contact, is described. A first conductor and a second...
US-6,784,551 Electronic device having a trimming possibility and at least one semiconductor chip and method for producing...
An electronic device has a semiconductor chip and a passive component, whose electrical values can be varied. The semiconductor chip is electrically conductively...
US-6,784,445 Apparatus for monitoring intentional or unavoidable layer depositions and method
The apparatus allows monitoring layer depositions in a process chamber. The apparatus has a light source, a sensor element, and at least one light detector. The...
US-6,784,105 Simultaneous native oxide removal and metal neutral deposition method
A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and...
US-6,784,091 Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices
A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks...
US-6,784,070 Intra-cell mask alignment for improved overlay
A method for intra-cell alignment of a substrate and mask comprises providing a substrate comprising an exposed photosensitive material, providing a phase-shift...
US-6,783,999 Subtractive stud formation for MRAM manufacturing
A method of fabricating a magnetic memory cell and an MRAM structure. A thin conductive hard is used to pattern a magnetic stack material layer. Conductive studs...
US-6,783,596 Wafer handling device
The present invention provides a wafer handling device having a base plate (G; G'), which has a first and a second supporting surface for a respective wafer (W1,...
US-6,783,372 Apparatus for connecting semiconductor modules
The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a...
US-6,783,284 Optical module for wavelength reference measurement in WDM systems
An optical for wavelength reference measurement has in essence an optical conductor with integrated fiber Bragg grating that has a transmission maximum at a...
US-6,782,491 Device and method for supplying power to computer peripheral equipment using the bus system of the computer
Apparatus and method for the power supply of auxiliary implements of computers via the bus system of the computer, wherein an energy store is provided within the...
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