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Patent # Description
US-6,829,185 Method for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memory
In a semiconductor memory, during the rewriting of the signal stored in a memory cell, a displacement current is produced in the cell capacitor, which has to be...
US-6,828,893 Transformer circuit arrangement
A transformer circuit arrangement has a first transformer (201) with a first lower limit frequency (fu1) and a first upper limit frequency (fo1), and a second...
US-6,828,814 Circuit configuration and display element
A circuit configuration has an integrated semiconductor element, preferably, an intelligent power semiconductor, and a display element. A display element...
US-6,828,680 Integrated circuit configuration using spacers as a diffusion barrier and method of producing such an...
In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer...
US-6,828,652 Fuse structure for semiconductor device
A fuse structure (30) formed in a semiconductor device is provided. The fuse structure (30) includes a layer of fuse material (32), a first contact (40), and a...
US-6,828,647 Structure for determining edges of regions in a semiconductor wafer
A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the...
US-6,828,609 High-voltage semiconductor component
A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone...
US-6,828,605 Field-effect-controlled semiconductor component and method of fabricating a doping layer in a vertically...
A field-effect-controllable semiconductor component has at least one source zone and at least one drain zone of a first conductivity type, and at least one body...
US-6,828,406 Method of producing organic semiconductors having high charge carrier mobility through .pi.-conjugated...
The organic polymers of the invention have electrical semiconductor properties. The compounds have a backbone of phenylene groups to which side groups with...
US-6,828,249 System and method for enhanced monitoring of an etch process
A method for monitoring an etch process of a substrate that includes receiving a first signal having a first wavelength, deriving a second signal based on the...
US-6,828,192 Semiconductor memory cell and method for fabricating the memory cell
A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner...
US-6,827,635 Method of planarizing substrates
A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The...
US-6,827,502 Twin VCSEL array for separate monitoring and coupling of optical power into fiber in an optical subassembly
The present invention provides a two VCSEL array mounted in a single can with a monitoring diode. One VCSEL is directed toward the can window (for coupling with...
US-6,826,111 On chip scrambling
A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells...
US-6,826,107 High voltage insertion in flash memory cards
A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at...
US-6,826,099 2T2C signal margin test mode using a defined charge and discharge of BL and /BL
A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit...
US-6,826,075 Random access semiconductor memory with reduced signal overcoupling
A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines...
US-6,826,037 Electronic structure
An electronic structure includes an electronic component, which is configured to be in electric contact with a base and has a mounting side configured for...
US-6,825,709 Temperature compensation circuit for a hall element
A temperature compensation circuit for a Hall element has a first and a second band gap reference circuit. The Hall element is fed from an excitation current...
US-6,825,707 Current mode logic (CML) circuit concept for a variable delay element
An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example,...
US-6,825,682 Test configuration for the functional testing of a semiconductor chip
A test configuration for the functional testing of a semiconductor chip is described. The semiconductor chip, which can be subjected to a functional test for the...
US-6,825,549 Electronic component with external flat conductors and a method for producing the electronic component
An electronic component with external flat conductors and a method producing the component includes placing the external flat conductors as waveguides with a...
US-6,825,514 High-voltage semiconductor component
A process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first...
US-6,825,116 Method for removing structures
A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying...
US-6,825,098 Method for fabricating microstructures and arrangement of microstructures
A method referred to as a "cellular damascene method" utilizes a multiplicity of regularly arranged closed cavities referred to as "cells", which are produced in...
US-6,825,096 Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors
An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment...
US-6,825,093 Process window enhancement for deep trench spacer conservation
In a process for manufacturing deep trench (32) memory cells, a method of enhancing the process window by better protecting the nitride spacer (52) prior to the...
US-6,825,079 Method for producing a horizontal insulation layer on a conductive material in a trench
In order to form an oxide cover on a conductive filling in a trench in a semiconductor substrate an HDP oxide is deposited on the conductive filling using a...
US-6,824,949 Polybenzoxazole precursors, photoresist solution, polybenzoxazole, and process for preparing a polybenzoxazole...
There are disclosed polybenzoxazole precursors which can be processed by centrifugal techniques, which can be cyclized to polybenzoxazoles on substrates without...
US-6,824,757 Method and arrangement for generating ultrapure steam
The invention relates to a method for generating ultrapure steam by oxidation of hydrogen in a closed torch with separate feed lines for hydrogen and oxygen and...
US-6,824,642 Phenyl-linked oxazole cyanates as dielectrics having good adhesive and filling properties
The following invention relates to phenyl-linked polybenzoxazoles having terminal, aryl- or heteroaryl-attached cyanate groups which can be used for adhesive...
US-6,824,456 Configuration for polishing disk-shaped objects
A polish head for Chemical Mechanical Polishing includes a backing film of silicone on a rigid support element, preferably, of amorphous ceramic. The silicone...
US-6,824,451 Process for the abrasive machining of surfaces, in particular of semiconductor wafers
A process is described for the chemical mechanical machining of semiconductor wafers. A plurality of surfaces are successively subjected to a polishing step, in...
US-6,823,713 Scanning tip orientation adjustment method for atomic force microscopy
A method of calibrating an AFM scanner head of an AFM machine to determine the arc functions of the scanner head are provided. A method of measuring the actual...
US-6,823,095 Optoelectronic device
An optoelectronic component has at least one monolithically integrated laser diode and at least one monolithically integrated optical waveguide. At least one of...
US-6,823,024 Compensation circuit and method for compensating for an offset
To demodulate a frequency-modulated signal having an offset, two time constants are provided in a filter unit. The filter unit has two analog or digital low-pass...
US-6,823,003 Multi-path transceiver amplification apparatus, method and system
A multi-path transceiver apparatus, method and system for implementation in a bidirectional antenna path by which a transceiver output signal is provided with a...
US-6,822,923 RAM memory circuit and method for controlling the same
A RAM memory circuit and method for controlling the same includes memory cells disposed in a matrix of rows and columns each addressed for writing in/reading out...
US-6,822,916 Read/write amplifier having vertical transistors for a DRAM memory
As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit...
US-6,822,913 Integrated memory and method for operating an integrated memory
An integrated memory includes memory cells arranged in a memory cell array and a read/write amplifier for evaluating and amplifying data signals of the memory...
US-6,822,891 Ferroelectric memory device
A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and...
US-6,822,872 Housing for receiving a component which can be connected to the housing in a pluggable manner
The invention pertains to housing for receiving a component which can be connected to the housing in a pluggable manner, in particular an optoelectronic...
US-6,822,692 Digital filter
Digital filter for filtering a digital input signal with a variable filter length (l), it being possible to switch over the filter length (l) of the digital...
US-6,822,597 Comparator circuit for mapping an analog input signal into a digital output signal
The invention is direct to a comparator circuit that maps an analog input signal into a digital output signal and comprises a threshold as well as an upper and a...
US-6,822,399 Half-bridge circuit
A half-bridge circuit includes: a vertically designed n-conducting first MOS transistor that is integrated in a first semiconductor body having a front side and...
US-6,822,301 Maskless middle-of-line liner deposition
A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes...
US-6,822,281 Trench cell for a DRAM cell array
A trench cell for use in a DRAM array includes a vertical selection transistor of a first conductivity type at the--seen in the bit line direction--first side of...
US-6,821,900 Method for dry etching deep trenches in a substrate
A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees...
US-6,821,894 CMP process
The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a...
US-6,821,865 Deep isolation trenches
A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation...
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