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MRAM configuration having selection transistors with a large channel width
The invention relates to an MRAM configuration that includes a selection transistor connected to several MTJ memory cells. The selection transistor has an...
Integrated circuit having electrical connecting elements
On a substrate, first and second electrical connecting elements of an integrated circuit are disposed next to one another along a first direction. The first...
Bipolar high-voltage power component
A bipolar high-voltage power component, in particular an IGBT, includes a semiconductor body on which at least two mutually spaced apart electrodes are provided,...
Fuse configuration with modified capacitor border layout for a
semiconductor storage device
A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first...
Electrostatic damage (ESD) protected photomask
A photomask (8) protected against electrostatic damage and a method of manufacturing such a photomask is disclosed. The photomask (8) comprises a transparent...
Heating system, method for heating a deposition or oxidation reactor, and
reactor including the heating system
A heating system, a method for heating a deposition reactor or an oxidation reactor, and a reactor utilizing the heating system are particularly suited for...
Circuit configuration for matching an amplifier to a radio-frequency line,
and use of the circuit configuration
A circuit for matching an amplifier to a radio-frequency line is described. In order to minimize the number of components required for matching the amplifier to...
Fuse concept and method of operation
It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on...
Alignment system and method using bright spot and box structure
There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is...
Integrated circuit with an analog amplifier
An integrated circuit includes an analog amplifier connected to a terminal pad and has a Miller compensation of a section of the analog amplifier. The Miller...
Method of frequency limitation and overload detection in a voltage
A regulated output voltage and an output current are generated by using a switching device for providing the output current and controlling the switching device...
Tracking circuit for tracking the voltage potential of an insulation well for the insulation of an integrated component (1) embedded in the insulation well, the...
Integrated circuit configuration having a structure for reducing a minority
charge carrier current
An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and...
Integrated circuit configuration and method of fabricating a dram structure
with buried bit lines or trench...
The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first...
Semiconductor circuit configuration and associated fabrication method
The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of...
Memory architecture with series grouped by cells
An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel....
Semiconductor component for connection to a test system
The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor...
Method for experimentally verifying imaging errors in photomasks
The method enables determining imaging errors of photomasks for the lithographic structuring of semiconductors. A latent image of the mask is first produced in a...
Data path calibration and testing mode using a data bus for semiconductor
A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device...
Integrated circuit with temperature sensor and method for heating the
A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least...
Integrated memory with a configuration of non-volatile memory cells and
method for fabricating and for...
An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive...
Clock signal generating device
A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished...
Shift register for sequential fuse latch operation
A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a...
High speed sense amplifier
A high-speed sense current amplifier with a low power consumption for a memory cell, the sense current amplifier having: a first current mirror circuit, which...
Apparatus for protecting an integrated circuit formed in a substrate and
method for protecting the circuit...
An apparatus for protecting an integrated circuit formed in a substrate and a method for protecting the integrated circuit against reverse engineering includes...
Connection of packaged integrated memory chips to a printed circuit board
An interface unit and a printed circuit board configuration includes at least two interface units for linking conventional commercially available packages of...
Lead frame, circuit board with lead frame, and method for producing the
A lead frame is described which has at least one integrated electronic circuit. The integrated electronic circuit is situated in a region of a main area of the...
Pin diode and method for fabricating the diode
The invention is a diode having at least one trench in the semiconductor substrate and insulation configured on the surface of the semiconductor substrate so...
Power semiconductor switch
An IGBT structure includes successive regions whose conductivities have alternating signs. The structure is dimensioned for punch-through and is provided with...
Semiconductor memory cell and semiconductor component as well as
manufacturing methods therefore
A semiconductor memory cell with a storage transistor, a selection transistor and a layer structure is provided. The layer structure is formed of at least two...
Field effect transistor
A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire...
Test wafer and method for producing the test wafer
A test wafer is provided, in particular for use in monitoring inspection installations for semiconductor fabrication that are based on the analysis of scattered...
Plasma-etching process for molybdenum silicon nitride layers on half-tone
phase masks based on gas mixtures...
A method for etching phase shift layers of half-tone phase masks includes etching a phase shift layer by using a plasma which is obtained from CH.sub.3 F and...
Process of fabricating DRAM cells with collar isolation layers
A process of preparing DRAM cells with collar isolation layers that isolate the trench top with vertical cell and active area from the buried plate to eliminate...
Process for depositing WSix layers on a high topography with a defined
Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten...
Method for manufacturing a buried strap contact in a memory cell
A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In...
Design and signal recovery of biomolecular sensor arrays
The present invention provides an apparatus and method of reducing noise associated with biomolecular measurement systems. Sensor detection system noise...
Process facility having at least two physical units each having a reduced
density of contaminating particles...
In a process facility for producing semiconductor wafers, a third physical unit is configured between two physical units that produce mini environments. The...
Method for generating a sequence of random numbers of A 1/f-noise
A computer programmed to process a method for generating a sequence of random numbers of a 1/f noise has the following steps: 1). Determining a constant step...
Circuit configuration for filtering a radio-frequency signal
A circuit configuration for filtering a radio-frequency signal, in particular, in tuners for television sets, includes a control signal connection for feeding in...
Driver circuit for driving voice and data signals from a switching center via a subscriber line (38) to a subscriber terminal, having: a controllable voice signal...
The non-volatile memory cell of a memory circuit includes at least one enhancement pMOS transistor having a floating gate. It further includes an enhancement...
Circuit arrangement for the storage of digital data
In order to make memories more secure against interference occurring in operation, error correction devices are normally associated with them. If the memory...
Memory integrated circuit
An improved memory IC whose memory cells are configured in a chain architecture is disclosed. The first diffusion regions of the cell transistors of the chain...
Method and system for bidirectional signal transmission
A system for bidirectional signal transmission of an electrical signal from a transmitter at a first location to a receiver at a second location, and from a...
Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive...
Apparatus and method for detecting an amount of depolarization of a
linearly polarized beam
An apparatus and a method for detecting an amount of depolarization of a linearly polarized beam transmitted by a birefringent medium in the direction of the...
Layering nitrided oxide on a silicon substrate
A process for producing a nitrided oxide layer on a silicon semiconductor substrate includes introducing a multiplicity of wafers into an atmospheric batch...
Three layer aluminum deposition process for high aspect ratio CL contacts
A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the...
MIM capacitor structures and fabrication methods in dual-damascene
A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned...