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Patent # Description
US-6,810,174 Optical filter and optical filtering method
An optical signal alternately traverses a total of n couplers and n-1 DGD units, arranged therebetween, with a differential group delay between two signal modes....
US-6,809,980 Limiter for refresh signal period in DRAM
The invention relates to a device (10) for outputting a refresh signal for a memory cell of a semiconductor memory device, the device (10) comprising: a...
US-6,809,978 Implementation of a temperature sensor to control internal chip voltages
A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit,...
US-6,809,972 Circuit technique for column redundancy fuse latches
Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of...
US-6,809,914 Use of DQ pins on a ram memory chip for a temperature sensing protocol
A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit that has a data pin, generating a temperature data...
US-6,809,894 Method and apparatus for handling end of data processing in a data storage device
A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write...
US-6,809,800 Apparatus for patterning a semiconductor wafer
An apparatus (100) for patterning the surface of a semiconductor wafer (130). A stage (148) is coupled to a motor (150) that is adapted to move the stage (148)...
US-6,809,601 Phase detector for a delay locked loop and delay locked loop with the phase detector
A phase detector for a delay locked loop with a delay unit that delays a periodic clock signal by a settable delay, has a first input for the periodic clock...
US-6,809,510 Configuration in which wafers are individually supplied to fabrication units and measuring units located in a...
A configuration for treating wafers in at least one clean room includes a configuration of production units and measuring units that receive wafers via a...
US-6,809,379 Field effect transistor and method for producing a field effect transistor
The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a...
US-6,809,361 Magnetic memory unit and magnetic memory array
A magnetic memory unit having a first magnetizable electrode, a second magnetizable electrode, and at least one nanotube arranged between the electrodes in a...
US-6,809,019 Method for producing a semiconductor structure, and use of the method
A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are...
US-6,809,005 Method to fill deep trench structures with void-free polysilicon or silicon
The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a...
US-6,807,514 Apparatus for monitoring the proper operation of components of an electrical system carrying out the same or...
The apparatus monitors several system components for proper operation. Each of the system components to be monitored is assigned at least one dedicated...
US-6,807,155 Method of profiling disparate communications and signal processing standards and services
A method of profiling disparate communications and signal processing standards. The method begins with selection of a set of communications and signal processing...
US-6,807,123 Circuit configuration for driving a programmable link
A circuit configuration for driving a programmable link has a volatile memory cell, which is coupled to the fuse for the permanent storage of data stored in the...
US-6,807,092 MRAM cell having frustrated magnetic reservoirs
A magnetoresistive random access memory (MRAM) cell, comprising a magnetic tunnel junction having frustrated magnetic reservoirs disposed oppositely along two...
US-6,807,089 Method for operating an MRAM semiconductor memory configuration
In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are...
US-6,807,084 FeRAM memory device
A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data...
US-6,807,064 Electronic component with at least one semiconductor chip and method for producing the electronic component
An electronic component having at least one semiconductor chip, a rewiring layer connected to the semiconductor chip, and a printed circuit board associated with...
US-6,806,785 Oscillator circuit using bonding wires for inductors and having a resonance transformation circuit
An oscillator circuit includes an oscillator core having two capacitances, two inductors designed as bonding wires, and a de-attenuation amplifier coupled to the...
US-6,806,752 Method and logic/memory module for correcting the duty cycle of at least one control/reference signal
A method and logic/memory module set the desired corrected duty cycle between the time periods of the first and second level states of at least one...
US-6,806,720 Method of reliability testing
A method of reliability testing is disclosed. A critical breakdown resistance of a device is determined. The test structure is subjected to stress conditions and...
US-6,806,694 Switching regulator with dynamic current limiting and drive circuit for the switching regulator
A switching regulator has a drive circuit, receiving an intermediate circuit input voltage, an output voltage of an intermediate circuit capacitor and an output...
US-6,806,579 Robust via structure and method
A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via...
US-6,806,562 Device with at least one semiconductor component and a printed circuit board and method of establishing an...
A device having a semiconductor component and a printed circuit board are described. The semiconductor component has external contacts and the printed circuit...
US-6,806,555 Semiconductor component and method for fabricating it
A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a...
US-6,806,550 Evaluation configuration for semiconductor memories
An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the...
US-6,806,533 Semiconductor component with an increased breakdown voltage in the edge area
A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an...
US-6,806,344 POLY-O-HYDROXAMIDE, POLYBENZOXAZOLE, AND ELECTRONIC COMPONENT INCLUDING A DIELECTRIC HAVING A BARRIER EFFECT...
Novel poly-o-hydroxyamides can be cyclized to give polybenzoxazoles which have a good diffusion barrier effect with respect to metals. The poly-o-hydroxyamides...
US-6,806,182 Method for eliminating via resistance shift in organic ILD
Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces...
US-6,806,152 Retrograde doped buried layer transistor and method for producing the same
An active transistor area with a retrograde doping area on a substrate in bipolar technology is produced by a method including the following steps: providing a...
US-6,806,124 METHOD FOR REDUCING THE CONTACT RESISTANCE IN ORGANIC FIELD-EFFECT TRANSISTORS BY APPLYING A REACTIVE...
A semiconductor device is fabricated and contains a first body made of an organic semiconductor material and a second body made of an electrically conductive...
US-6,806,121 Interconnect structure for an integrated circuit and corresponding fabrication method
The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1'; B1"), which is composed of a...
US-6,806,106 Bond wire tuning of RF power transistors and amplifiers
A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an...
US-6,806,097 Method for fabricating ferroelectric memory cells
Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a...
US-6,806,096 Integration scheme for avoiding plasma damage in MRAM technology
A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the...
US-6,806,037 Method for producing and/or renewing an etching mask
An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed...
US-6,806,027 CHEMICALLY AMPLIFIED PHOTORESIST AND PROCESS FOR STRUCTURING SUBSTITUENTS USING TRANSPARENCY ENHANCEMENT OF...
Chemically amplified photoresists exhibit increased transparency at a wavelength of 157 nm. The chemically amplified photoresist includes a polymer containing...
US-6,806,008 Method for adjusting a temperature in a resist process
A test reticle having a pad and antenna structures with varying critical dimensions is provided to measure sidewall angles developing in the resist sidewalls of...
US-6,805,568 Zipper connector
A connector arrangement comprises first conductor teeth on a first support and second conductor teeth on a second support. A slider is provided for electrically...
US-6,804,851 Holder for semiconductor wafers in a brush-cleaning installation
A holder in a brush-cleaning installation, preferably for combined use in the brush-cleaning and centrifugal-drying process, contains a carrier part from which...
US-6,804,519 Forward link inter-generation soft handoff between 2G and 3G CDMA systems
In a CDMA cellular radiotelephone system, a soft handoff (SHO) is performed when a mobile station communicates with a new inter-generation base station, without...
US-6,804,166 Method and apparatus for operating a semiconductor memory at double data transfer rate
A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a...
US-6,804,165 Latency time switch for an S-DRAM
Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data...
US-6,804,160 Memory device and method of accessing a memory device
A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory...
US-6,804,121 Housing for biometric sensor chips and method for producing the housing
A housing for biometric sensor chips and a method for producing such a housing includes a freely accessible fingerprint checking area on a sensor chip, a mount...
US-6,803,870 Procedure and device for analog-to-digital conversion
During A/D conversion of time-discrete analog input values, a quantizer is used in which an analog quantization error is obtained after every conversion. The...
US-6,803,629 Vertical field-effect transistor with compensation zones and terminals at one side of a semiconductor body
A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second...
US-6,803,627 Reverse-blocking power semiconductor component having a region short-circuited to a drain-side part of a body zone
A reverse-blocking power semiconductor component includes a drift path subdivided into a source-side area and a drain-side area by a region with opposite doping....
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