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Patent # Description
US-6,823,024 Compensation circuit and method for compensating for an offset
To demodulate a frequency-modulated signal having an offset, two time constants are provided in a filter unit. The filter unit has two analog or digital low-pass...
US-6,823,003 Multi-path transceiver amplification apparatus, method and system
A multi-path transceiver apparatus, method and system for implementation in a bidirectional antenna path by which a transceiver output signal is provided with a...
US-6,822,923 RAM memory circuit and method for controlling the same
A RAM memory circuit and method for controlling the same includes memory cells disposed in a matrix of rows and columns each addressed for writing in/reading out...
US-6,822,916 Read/write amplifier having vertical transistors for a DRAM memory
As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit...
US-6,822,913 Integrated memory and method for operating an integrated memory
An integrated memory includes memory cells arranged in a memory cell array and a read/write amplifier for evaluating and amplifying data signals of the memory...
US-6,822,891 Ferroelectric memory device
A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and...
US-6,822,872 Housing for receiving a component which can be connected to the housing in a pluggable manner
The invention pertains to housing for receiving a component which can be connected to the housing in a pluggable manner, in particular an optoelectronic...
US-6,822,692 Digital filter
Digital filter for filtering a digital input signal with a variable filter length (l), it being possible to switch over the filter length (l) of the digital...
US-6,822,597 Comparator circuit for mapping an analog input signal into a digital output signal
The invention is direct to a comparator circuit that maps an analog input signal into a digital output signal and comprises a threshold as well as an upper and a...
US-6,822,399 Half-bridge circuit
A half-bridge circuit includes: a vertically designed n-conducting first MOS transistor that is integrated in a first semiconductor body having a front side and...
US-6,822,301 Maskless middle-of-line liner deposition
A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes...
US-6,822,281 Trench cell for a DRAM cell array
A trench cell for use in a DRAM array includes a vertical selection transistor of a first conductivity type at the--seen in the bit line direction--first side of...
US-6,821,900 Method for dry etching deep trenches in a substrate
A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees...
US-6,821,894 CMP process
The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a...
US-6,821,865 Deep isolation trenches
A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation...
US-6,821,863 Method for producing a cavity in a monocrystalline silicon substrate and a semiconductor component having a...
A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper...
US-6,821,861 Method for fabricating an electrode arrangement for charge storage
The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided...
US-6,821,706 Polymerizable composition, polymer, resist, and process for electron beam lithography
A polymerizable composition for use in electron beam lithography, according to the following structural formula: ##STR1## The formula use the following...
US-6,821,693 Method for adjusting a multilevel phase-shifting mask or reticle
A method for adjusting (aligning) a multilevel phase-shifting mask or a multilevel phase-shifting reticle with the aid of at least one alignment mark provided on...
US-6,821,187 Method for chemical-mechanical polishing of a layer which is a substrate and is a metal selected from a...
The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the...
US-6,820,197 Data processing system having configurable components
The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the...
US-6,819,627 Method for storing data, method for reading data, apparatus for storing data and apparatus for reading data
The invention relates to two methods for reading and two methods for storing data, and also to an apparatus for compressing data and decompressing data which are...
US-6,819,625 Memory device
A memory device has a memory module, a controller, a data bus for connecting the controller and the memory module, a read clock generator, and a read clock bus...
US-6,819,624 Latency time circuit for an S-DRAM
Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data...
US-6,819,606 Method for storing data in a memory device with the possibility of access to redundant memory cells
A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step...
US-6,819,227 Acoustic signal generator, and method for generating an acoustic signal
An acoustic signal generator, and a method for generating an acoustic signal are described. The acoustic signal generator has a membrane that can oscillate, a...
US-6,819,147 Current sample-and-hold-circuit, a/d converter and a method for operating a current sample-and-hold circuit
The invention relates to a current sample-and-hold circuit comprising several sub-circuits, in which a current signal is stored. At least one of said...
US-6,819,142 Circuit for transforming a differential mode signal into a single ended signal with reduced standby current...
An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended...
US-6,819,089 Power factor correction circuit with high-voltage semiconductor component
A switching power supply including a power factor correction circuit comprises a rectifier, an inductor coupled in series with the rectifier, a semiconductor...
US-6,818,534 DRAM having improved leakage performance and method for making same
A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises...
US-6,818,519 Method of forming organic spacers and using organic spacers to form semiconductor device features
A method of forming organic spacers using an N.sub.2 plasma or N.sub.2 containing plasma anisotropic etchant, and using such organic spacers for forming features...
US-6,818,503 Method for fabricating a semiconductor memory device
A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor...
US-6,818,470 Process for producing a thermoelectric converter
Method for fabricating a thermoelectric converter having a plurality of series-connected thermoelement cells, which are connected in series with one another by...
US-6,818,090 Semiconductor device in chip format and method for producing it
A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is...
US-6,816,924 System and method for tracing ATM cells and deriving trigger signals
A trace and debug support unit (120) that works in conjunction with a bus sniffer (112). The trace and debug support unit (120) maintains in memory one or more...
US-6,816,876 Apparatus and method for modifying an M-sequence with arbitrary phase shift
An embodiment of the invention described in the specification and drawings is an apparatus and method of generating a phase-shifted maximum length pseudo-random...
US-6,816,432 Integrated semiconductor circuit having transistors that are switched with different frequencies
It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage....
US-6,816,406 Magnetic memory configuration
A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed...
US-6,816,328 Pseudo-synchronous interpolated timing recovery for a sampled amplitude read channel
Systems and methods for reading information stored on a magnetic medium are described. Data symbols are generated from a signal encoded at a baud rate with data...
US-6,816,094 Circuit configuration for the bit-parallel outputting of a data word
A circuit configuration for the bit-parallel outputting the bits of a data word includes at least two signal lines for feeding the data signals representing the...
US-6,816,024 Oscillator circuit with switchable compensated amplifiers
An oscillator circuit is specified, having an LC resonator, to which two or more current paths are connected, which are connected in parallel with one another...
US-6,815,803 Multiple chip semiconductor arrangement having electrical components in separating regions
A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted...
US-6,815,769 Power semiconductor component, IGBT and field-effect transistor
A trench power semiconductor component, in particular an IGBT, has an electrode (4) in a trench (3) that is laterally divided into a section (10) that serves as...
US-6,815,643 Semiconductor device with temperature regulation
A semiconductor device is described in which an integrated circuit executes dummy operating cycles in order to generate heat if the temperature of the ...
US-6,815,367 Elimination of resist footing on tera hardmask
A process of eliminating resist footing on a hardmask when preparing a semiconductor wafer stack, comprising: a) depositing a layer of hardmask material on a...
US-6,815,364 Tungsten hard mask
Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of...
US-6,815,317 Method to perform deep implants without scattering to adjacent areas
A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the...
US-6,815,248 Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed...
A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114),...
US-6,815,244 Methods for producing a thermoelectric layer structure and components with a thermoelectric layer structure
A method produces a thermoelectric layer structure on a substrate and the thermoelectric layer structure has at least one electrically anisotropically conductive...
US-6,815,234 Reducing stress in integrated circuits
A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress...
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