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Patent # Description
US-6,864,730 Clocked integrated semiconductor circuit and method for operating such a circuit
An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is...
US-6,864,671 Direct current voltage converter with switching regulator
A direct current voltage converter comprises a unit (BGR) for preparing a reference voltage (Vref), a regulator (OP), a pulse width modulator (Comp, Vsw), a...
US-6,864,619 Piezoelectric resonator device having detuning layer sequence
A resonator device includes a piezoelectric resonator having a detuning layer sequence arranged on the piezoelectric resonator. The detuning layer sequence...
US-6,864,575 Electronic interface structures and methods
Electronic component, in particular a chip, which can be electrically bonded by means of a plurality of contacts provided on the component to mating contacts...
US-6,864,535 Controllable semiconductor switching element that blocks in both directions
The controllable semiconductor switching element blocks in both directions. The semiconductor switching element is formed with a first conduction region and a...
US-6,864,528 Integrated, tunable capacitor
An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal...
US-6,864,188 Semiconductor configuration and process for etching a layer of the semiconductor configuration using a...
To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or...
US-6,864,182 Method of producing large-area membrane masks by dry etching
Based upon an existing or to be produced multi-layered semiconductor-insulator-semiconductor carrier layer wafer (SOI substrate), irregularity of the etching...
US-6,864,175 Method for fabricating integrated circuit arrangements, and associated circuit arrangements, in particular...
The invention relates to a method in which an eclectically nonconductive mask layer is applied to an electrically conductive contact layer which is supported by...
US-6,864,171 Via density rules
Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a...
US-6,864,170 Compact semiconductor structure
A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor...
US-6,864,151 Method of forming shallow trench isolation using deep trench isolation
A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating...
US-6,864,129 Double gate MOSFET transistor and method for the production thereof
A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed...
US-6,863,769 Configuration and method for making contact with the back surface of a semiconductor substrate
A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a...
US-6,862,702 Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices
The novel address counter can be used in combination with an existing test unit--serving for testing digital circuits--for addressing synchronous high-frequency...
US-6,862,238 Memory system with reduced refresh current
The present invention is a random access memory device with reduced refresh current and method for use in the same. The memory device includes a memory array...
US-6,862,234 Method and test circuit for testing a dynamic memory circuit
Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a...
US-6,861,872 Voltage down converter for low voltage operation
A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage...
US-6,861,723 Schottky diode having overcurrent protection and low reverse current
The invention relates to a Schottky diode in which p-doped regions (4, 5) are incorporated in the Schottky contact area. At least one (5) of these regions (4, 5)...
US-6,861,706 Compensation semiconductor component
A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the...
US-6,861,688 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with...
A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory...
US-6,861,560 Bis-o-aminophenols and processes for producing bis-o-aminophenols
A bis-o-aminophenol has a formula I ##STR1## These bis-o-aminophenols permit the preparation of polybenzoxazoles stabilized at high temperatures. The...
US-6,861,479 Composition and process for the production of a porous layer using the composition
Production of a porous layer includes using a composition which includes a first polymer component and a second polymer component, the first polymer component...
US-6,861,331 Method for aligning and exposing a semiconductor wafer
Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the...
US-6,861,312 Method for fabricating a trench structure
An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to...
US-6,861,291 Method producing a contact connection between a semiconductor chip and a substrate and the contact connection
A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The...
US-6,861,206 Method for producing a structured layer on a semiconductor substrate
A method for producing a structured layer on a semiconductor substrate includes the steps of creating the layer on the substrate, modifying a surface of the...
US-6,860,563 Device for preventing or reducing tipping of the head
A description is given of a device for avoiding or limiting the tilting of the head forwards and/or to the side of a passenger sitting in a seat which has a...
US-6,859,873 Variable length instruction pipeline
A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline...
US-6,859,489 Method and device for determining the carrier frequency of base stations in the mobile receiver of a cellular...
The method and device enable determining the carrier frequency of base stations in the mobile receiver of a cellular mobile radio system working with W-CDMA. The...
US-6,859,411 Circuit and method for writing and reading data from a dynamic memory circuit
A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit...
US-6,859,407 Memory with auto refresh to designated banks
A memory comprising 2.sup.n dynamic random access memory (DRAM) banks, wherein n is an integer greater than or equal to 2, 2.sup.n refresh row address counter...
US-6,859,406 Dynamic RAM semiconductor memory and method for operating the memory
A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are...
US-6,859,398 Semiconductor memory component
A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a...
US-6,859,153 Method and apparatus for changing the rate of time-discrete signals
Methods and apparatus are provided for changing the rate of time-discrete signals. When changing the rate or for the interpolation of time-discrete input values...
US-6,859,011 Method for controlling the charging and discharging phases of a backup capacitor and a circuit configuration...
A method for controlling the charging and discharging phases of a backup capacitor for a data storage medium has the step where the backup capacitor is first...
US-6,858,895 Circuit configuration having a field-effect transistor operable at higher frequencies
A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second...
US-6,858,890 Ferroelectric memory integrated circuit with improved reliability
An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is...
US-6,858,799 Electronic component with a semiconductor chip and method of producing the electronic component
An electronic component includes a semiconductor chip that has an active upper side with integrated circuits and a passive rear side. The rear side and the side...
US-6,858,492 Method for fabricating a semiconductor memory device
Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration...
US-6,858,449 Process and device for the abrasive machining of surfaces, in particular semiconductor wafers
A process for abrasive machining of surfaces of semiconductor wafers, in particular during the production of electronic memory elements, is described. In the...
US-6,858,447 Method for testing semiconductor chips
A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is...
US-6,858,445 Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an...
The present invention provides a method for optimizing the overlay adjustment of two mask planes in a photolithographic process for the production of an...
US-6,858,442 Ferroelectric memory integrated circuit with improved reliability
A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion...
US-6,858,441 MRAM MTJ stack to conductive line alignment method
A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a...
US-6,858,376 Process for structuring a photoresist layer on a semiconductor substrate
In a negative or positive photoresist layer structured with the aid of the customary lithography technique, the photoresist layer is heated briefly, in the...
US-6,857,841 Vehicle for transporting a semiconductor device carrier to a semiconductor processing tool
A vehicle for transporting semiconductor devices is used for servicing loadports of semiconductor processing tools with device carriers by use of a portal hoist....
US-6,857,791 Optical device assembly with an anti-kink protector and transmitting/receiving module
An optical device assembly includes an optical device. The optical device has an optical fiber led from the device with an anti-kink protector, and also a...
US-6,857,789 Coupling configuration for coupling an optical plug with a plug pin to a mounting tubelet
A coupling configuration enables the coupling of an optical plug with a plug pin to a mounting tubelet wherein at least one optical conductor is arranged in at...
US-6,857,091 Method for operating a TAP controller and corresponding TAP controller
The present invention provides a method for operating a TAP controller having a first input terminal (Etms) for inputting a logic test mode selection signal...
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