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Patent # Description
US-6,973,205 Scratch-resistant coating for a semiconductor component
To increase the scratch resistance of a surface passivation, in particular, for fingerprint sensors, a antifrictional layer is applied to reduce the shearing...
US-6,973,181 Method of generating a ring signal in a subscriber line interface circuit technical field
In a method and a device for controlling the magnitude of the generated ring signal in a the Subscriber Line Interface Circuit (SLIC) the voltage of the A and B...
US-6,973,110 Monolithic laser configuration
A monolithic laser configuration has a substrate, a laser diode disposed on the substrate for generating a light beam, a photodetector disposed on the substrate...
US-6,973,008 Apparatus for flexible deactivation of word lines of dynamic memory modules and method therefor
An apparatus and a method are proposed, which can be used to delay a deactivation of a row address in the event of repeated access to a bank of an RLDRAM memory...
US-6,972,983 Increasing the read signal in ferroelectric memories
Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example,...
US-6,972,981 Semiconductor memory module
The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command...
US-6,972,832 Method of grounding a photoblank to a holding device
A retaining device for photo blanks, comprising a retaining member (1) with a supporting surface (3) for a photo blank (4) and a ground element (10) which can be...
US-6,972,701 A/D converter calibration
A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means...
US-6,972,641 FBAR ladder filter and method of grounding of FBAR ladder filters
A FBAR ladder filter which may yield less degradation in the stopband near the passband edges than conventionally grounded FBAR ladder filters. For that purpose...
US-6,972,613 Fuse latch circuit with non-disruptive re-interrogation
Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the...
US-6,972,600 Base element for a multiplexer structure and corresponding multiplexer structure
A divided multiplexer structure which can be used to replace a tristate bus, comprising node elements which are embodied in such a way that no feedback can occur...
US-6,972,595 Electrical circuit
An electrical circuit assembly includes a node and an electrical circuit. The circuit draws a node point to a specific potential when and for as long as the node...
US-6,972,549 Bandgap reference circuit
A bandgap reference circuit is provided in which the conventional current loop with a current mirror for feeding a differential amplifier is replaced by a...
US-6,972,518 Device having a protective seal for emitting electromagnetic radiation and process for producing the device
A device for emitting electromagnetic radiation includes a substrate, at least one active layer of a radiation-emitting organic material, a cover, and a seal...
US-6,972,469 Lateral PIN diode and method for processing same
A PIN diode includes a first p-area, an n-area, and in between an intermediate area on a first surface of a substrate, wherein a doping concentration of the...
US-6,972,427 Switching device for reconfigurable interconnect and method for making the same
A switching device to be reversibly switched between an electrically isolating off-state and an electrically conducting on-state for use in, e.g., a...
US-6,972,266 Top oxide nitride liner integration scheme for vertical DRAM
A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical...
US-6,972,226 Charge-trapping memory cell array and method for production
In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of...
US-6,972,069 Device and method for connecting two wafers in a planar manner for grinding down and cutting up a product wafer
A device for connecting two wafers in a planar manner for grinding down and cutting up a product wafer has a vacuum chamber, a chuck for receiving a carrier...
US-6,971,519 Configuration of a flat carrier with a chip module in a padded envelope and method of arranging the configuration
A configuration of a flat carrier with a chip module in a padded envelope, which can be transported in a transport device in the direction of one of the...
US-6,971,039 DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second...
A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides...
US-6,970,899 Calculating unit and method for subtracting
Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass...
US-6,970,589 Method for inspecting defects on a mask
The whole-area defect inspection of masks is made possible by interconnecting two otherwise independent defect inspection systems via a powerful bus system or...
US-6,970,558 Method and device for suppressing noise in telephone devices
Device and method for noise suppression in telephone equipment, in particular with hands-free equipment, having a level discriminator, an additional filter with...
US-6,970,395 Memory device and method of reading data from a memory device
A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The...
US-6,970,390 DRAM memory circuit with sense amplifiers
In a DRAM memory circuit, the sense amplifiers, for amplifying the differential voltage sensed between the cores of a bit line, in each case contain two...
US-6,970,389 Integrated memory
An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals...
US-6,970,046 Digital phase-locked loop
A digital phase-locked loop with a digitally controlled oscillator is disclosed. The phase difference between a reference phase and a phase derived from the...
US-6,970,016 Data processing circuit and method for transmitting data
Data processing circuit including a single rail bus having a single rail line, a dual rail bus having a first dual rail line for data bits and a second dual rail...
US-6,970,006 Apparatus for the automated testing, calibration and characterization of test adapters
The apparatus enables the automated testing, calibration and characterization of test adapters for semiconductor devices. A holder for the test adapter can be...
US-6,969,917 Electronic chip component with an integrated circuit and fabrication method
The invention relates to an electronic chip component and a method for fabricating the chip component with a semiconductor chip having an integrated circuit...
US-6,969,905 Leadframe for semiconductor chips and electronic devices and production methods for a leadframe and for...
A leadframe for semiconductor chips and electronic devices produced on the leadframe includes providing the leadframe with a basic substrate, on which are...
US-6,969,863 Arrangement for feeding or dissipating heat to/from a semiconductor substrate for the purpose of preparing or...
The arrangement comprises a hot or cool plate (12) that has a substantially planar surface for accommodating the semiconductor substrate and for transmitting...
US-6,969,265 Electrically connecting integrated circuits and transducers
Apparatus and methods of electrically connecting integrated circuits and transducers are described. In particular, a transducer includes a base mountable on a...
US-6,968,544 Method for transformation of interface definitions and intermediate format tables thereof
A method for converting interface definitions within a source code program into an intermediate format includes identifying with a computer system objects in a...
US-6,968,518 Method of resolving missing graphical symbols in computer-aided integrated circuit design
A system and method is presented for resolving missing graphical symbols in computer-aided design of integrated circuits during schematic migration. The system...
US-6,968,483 Circuit and method for testing a data memory
A data memory to be tested is connected to a processing unit. Data items to be stored are produced from a test pattern data item in the processing unit and are...
US-6,968,481 Method and device for adapting/tuning signal transit times on line systems or networks between integrated circuits
A method and a device adapt/tune signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine...
US-6,968,049 Transmission of charging signals on a data transmission path
An apparatus for transmitting charging signals on a data transmission path having a line impedance includes a driver device for setting a line voltage level that...
US-6,967,999 Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks
An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal...
US-6,967,893 Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory
An integrated synchronous memory has a register which can store a frequency-range information item regarding whether the memory is operated in a first or in a...
US-6,967,606 Loop filter for a continuous time sigma delta analog to digital converter
A loop filter for a continuous time sigma delta analog to digital converter which converts an analog input signal into a digital output signal, said loop filter...
US-6,967,370 Integrated semiconductor circuit having a multiplicity of memory cells
An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are...
US-6,967,147 Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor
Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen...
US-6,967,133 Method for fabricating a semiconductor structure
The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor...
US-6,966,496 Chip module
The chip module comprises a semiconductor chip, which is fixed on a main side of a substrate of planar extent. A component, which is provided for taking up,...
US-6,965,910 Calculating unit and method for adding
A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder...
US-6,965,809 Method for characterizing and simulating a chemical mechanical polishing process
A method for characterizing and simulating a CMP process, in which a substrate to be polished, in particular a semiconductor wafer, is pressed onto a polishing...
US-6,965,660 Digital phase-locked loop
A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock...
US-6,965,535 Integrated semiconductor memory circuit and a method for operating the same
An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and...
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