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Patent # Description
US-6,840,808 Connector for a plurality of switching assemblies with compatible interfaces
A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching...
US-6,840,778 Contact base with detachable contacts for making electrical contact with an electronic component, in particular...
A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic...
US-6,840,684 Housing for a coupling configuration for injecting and/or extracting optical signals
A housing for a coupling configuration for injecting or extracting optical signals of at least one optical data channel into or from an optical conductor has a...
US-6,839,962 Method of producing micromechanical structures
A micromechanical structure is described which is disposed on a base body and requires protection from environmental influences by a covering body. Furthermore,...
US-6,839,397 Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits
A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage...
US-6,839,298 Zero static power fuse cell for integrated circuits
A fuse cell with reduced or no static power dissipation is disclosed. The fuse cell utilizes a latch to store the state of the fuse. The use of the latch avoids...
US-6,839,288 Latch scheme with invalid command detector
Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced...
US-6,839,287 Method of storing a quantity of data in a target memory location and storage system
In a method of storing a quantity of data in a target memory location, the data quantity is stored first in a non-volatile buffer memory location. It is then...
US-6,839,267 Structure and method of multiplexing bitline signals within a memory array
An integrated circuit memory is provided in which a multiplexer is operable to select one of a plurality of bitlines to couple to a master bitline using select...
US-6,839,241 Circuit module
A circuit module comprises a circuit board having a plurality of contact elements along a longitudinal edge thereof. The circuit board has arranged thereon a...
US-6,839,220 Multi-layer barrier allowing recovery anneal for ferroelectric capacitors
A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer...
US-6,838,922 Circuit arrangement for generating non-overlapping clock phases
A circuit arrangement for generating non-overlapping clock phases including a first circuit, a second circuit, and a multiplexer. The first circuit combines two...
US-6,838,917 Circuit configuration for processing data, and method for identifying an operating state
A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship...
US-6,838,746 Semiconductor configuration and method for fabricating the configuration
The invention proposes a semiconductor configuration having a substrate, which has at least one component integrated therein. The substrate has a first main side...
US-6,838,729 Semiconductor component with enhanced avalanche ruggedness
The invention relates to a semiconductor component with enhanced avalanche ruggedness. At the nominal current of this semiconductor component, in the event of an...
US-6,838,724 Transistor array and semiconductor memory configuration fabricated with the transistor array
A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of...
US-6,838,339 Area-efficient stack capacitor
An area-efficient stack capacitor for use in an integrated circuit comprises, in one embodiment, a layer of elemental platinum (Pt) as a bottom electrode, a...
US-6,838,335 Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an...
A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation...
US-6,838,334 Method of fabricating a buried collar
A method of forming a buried collar on the sidewall of a trench in a semiconductor substrate including: (a) providing the trench in the semiconductor substrate,...
US-6,838,216 Photolithographic mask and methods for producing a structure and of exposing a wafer in a projection apparatus
Auxiliary openings are assigned to openings on a mask to be transferred to a wafer. These auxiliary openings have a phase-shifting property, preferably between...
US-6,838,212 Method for producing scatter lines in mask structures for fabricating integrated electrical circuits
In the method according to the invention, scatter lines (2, 3, 4, 5, 6, 7, 8) with a predetermined width are produced, which run at a predetermined distance from...
US-6,836,953 Method of producing a biometric sensor
In a biometric sensor and a method for its production, a sensor chip is provided with connecting contacts in the form of electrically conductive bumps. The...
US-6,836,866 Circuit including a built-in self-test
A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface....
US-6,836,500 Semiconductor laser chip and method for fabricating a semiconductor laser chip
A semiconductor laser chip has a semiconductor laser element and a beam shaper integrated into the semiconductor laser chip and serving for shaping a laser beam...
US-6,836,451 Lensless optical servo system for an optically assisted disk drive
A lensless optical servo system has an unfocused light source and patterned photodetectors. The unfocused light is reflected by markings on a rotating disk and...
US-6,836,440 Method of checking electrical connections between a memory module and a semiconductor memory chip
Two methods check functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts...
US-6,836,208 Contactless data transmission system and method for contactless data transmission
A contactless data transmission system having a transponder and a write/read station, between which data can be exchanged by a HF signal. The transponder...
US-6,836,188 PLL circuit and method for eliminating self-jitter in a signal which is received by a control circuit
PLL circuit for eliminating self-jitter in a signal which is received by a control circuit, having a phase comparison circuit for producing a phase difference...
US-6,836,162 Method and arrangement for frequency doubling
To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to...
US-6,836,137 Configuration for testing semiconductor devices
A current measuring device in the form of a Hall sensor device is disposed in an individual current/voltage supply line device with a common current/voltage...
US-6,835,666 Method for fabricating a mask for semiconductor structures
A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second...
US-6,835,663 Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity
A process of using a-C:H layer as a hardmask material with tunable etch resistivity in a RIE process that alleviates the addition of a layer forming gas to the...
US-6,835,612 Method for fabricating a MOSFET having a very small channel length
A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective...
US-6,835,528 Fluorine-containing photoresist having reactive anchors for chemical amplification and improved...
A photoresist which has high transparency at a wavelength of 157 nm and which therefore permits a greater layer thickness in photolithographic processes for the...
US-6,835,508 Large-area membrane mask and method for fabricating the mask
In order to increase the rigidity of a membrane mask that can be used for ion projection lithography, a second wafer made of the material of the membrane layer...
US-6,835,506 Method for producing a photomask and corresponding photomask
The present invention provides a method for producing a photomask (1), which has the following steps: provision of a mask blank with a substrate (1a) and a...
US-6,835,456 Antireflective, layer-forming composition, layer configuration containing the antireflective layer, and process...
A layer-forming antireflective composition is proposed which contains as a base polymer poly(hydroxyamide) or polybenzoxazole and as dye component at least one...
US-6,835,417 Method and device for depositing thin layers via ALD/CVD processes in combination with rapid thermal processes
The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged...
US-6,834,377 Method for checking an integrated electrical circuit
A layout of an integrated electrical circuit on a memory unit of a computer system includes one or more instantiations of at least one circuit network ...
US-6,834,108 Method for improving acoustic noise attenuation in hand-free devices
The present invention relates to a method for improving acoustic noise attenuation, in which the method includes an adaptive control for partial-band echo...
US-6,833,802 Controllable electrical resistor
The invention is based on the object of specifying a controllable resistor network which exhibits a wide dynamic range and at the same time only a small relative...
US-6,833,745 Signal generator for charge pump in an integrated circuit
The invention relates to a signal generating device (10) for a charge pump for an integrated circuit, comprising: N signal outputs D.sub.1, . . . , D.sub.N and a...
US-6,833,731 Electronic circuit for a method for storing information, said circuit comprising ferroelectric flip-flops
A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic...
US-6,833,728 Simultaneous bidirectional signal transmission
A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for...
US-6,833,584 Trench power semiconductor
A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall,...
US-6,833,324 Process and device for cleaning a semiconductor wafer
A surface of a semiconductor wafer is cleaned following a chemical mechanical polishing process. With the semiconductor wafer rotating continuously, an...
US-6,833,302 Method for fabricating a memory cell
A method for fabricating a memory cell, in particular, a DRAM memory cell, having a transistor and a trench capacitor that are connected to one another through a...
US-6,833,298 Method for fabricating a semiconductor component having at least one transistor cell and an edge cell
The present invention relates to a method for fabricating a semiconductor component having at least one transistor cell and an edge cell. The method includes...
US-6,831,686 Method and device for the exposure-dependent noise correction in image sensors which can be addressed in lines...
Method and device for the exposure-dependent noise correction in images sensor which can be addressed in lines and columns are converted into digital values and...
US-6,831,586 Comparator circuit and method of operating a comparator circuit
A comparator for an analog-to-digital converter comprises an input stage (in.sub.+, in.sub.-, M1, M2) for receiving an input signal; a bipolar latch stage (Q1,...
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