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Patent # Description
US-6,853,206 Method and probe card configuration for testing a plurality of integrated circuits in parallel
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test...
US-6,853,085 Method and device for securing a multi-dimensionally constructed chip stack and chip configuration
A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and...
US-6,853,025 Trench capacitor with buried strap
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which...
US-6,853,023 Semiconductor memory cell configuration and a method for producing the configuration
A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory...
US-6,853,000 Test structure for determining a doping region of an electrode connection between a trench capacitor and a...
A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a...
US-6,852,931 Configuration having an electronic device electrically connected to a printed circuit board
A configuration and also a method for the configuration in which, the configuration has at least one electronic device with associated contact connections and at...
US-6,852,640 Method for fabricating a hard mask
The method is for producing a hard mask on a substrate, and in particular, on a primary area of a semiconductor substrate. The method includes the following...
US-6,852,639 Etching processing method for a material layer
The present invention provides a processing method that changes the given and unfavorable surface contour of a material layer to a predetermined, more favorable...
US-6,852,638 Selective base etching
A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of ...
US-6,852,628 Method of insulating interconnects, and memory cell array with insulated interconnects
The process is used to electrically insulate adjacent metallic interconnects made from an aluminum-containing alloy, in particular for interconnects which are...
US-6,852,598 Method for the fabrication of a DMOS transistor
A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure,...
US-6,852,585 Semiconductor circuit arrangement and a method for producing same
A semiconductor circuit arrangement includes a circuit element embedded in a semiconductor substrate of a first conductivity type in an integrated manner and is...
US-6,852,567 Method of assembling a semiconductor device package
A method of assembling a semiconductor device package includes first attaching a semiconductor device to a die-pad area of a leadframe. Electrical connections...
US-6,852,473 Anti-reflective coating conformality control
A method for forming an anti-reflective coating on a semiconductor substrate, including providing a first vessel containing an anti-reflective coating component...
US-6,852,240 Method of manufacturing a ferroelectric capacitor configuration
A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms...
US-6,851,598 Electronic component with a semiconductor chip and method for producing the electronic component
An electronic component with at least one semiconductor chip and a wiring layer are described. The wiring layer has elastic contact elements of low mechanical...
US-6,850,451 Zero static power fuse for integrated circuits
A fuse cell with reduced or no static power dissipation is disclosed. The fuse cell utilizes a latch to store the state of the fuse. The use of the latch avoids...
US-6,850,448 Temperature-dependent refresh cycle for DRAM
A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a...
US-6,850,420 Flat mount with at least one semiconductor chip
The flat mount assembly, or transponder, has at least one semiconductor chip that is connected to an antenna for interchanging data and power with an electronic...
US-6,850,414 Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor...
An electronic printed circuit board has a memory module and a contact strip for insertion into another electronic unit. The memory module has at least nine...
US-6,850,111 Charge pump circuit
A charge pump circuit provides an output voltage greater than a supply voltage of the charge pump circuit. The charge pump circuit has a first and a second...
US-6,850,099 Scalable driver device and related integrated circuit
In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal,...
US-6,849,893 Semiconductor circuit structure and method for fabricating the semiconductor circuit structure
A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching...
US-6,849,496 DRAM with vertical transistor and trench capacitor memory cells and method of fabrication
A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A...
US-6,849,495 Selective silicidation scheme for memory devices
A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide...
US-6,849,465 Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition
A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic...
US-6,849,365 Reflection mask for EUV-lithography and method for fabricating the reflection mask
A reflection mask has a multilayer reflection layer for the reflection of radiated-in radiation by constructive interference of the reflected partial beams and a...
US-6,849,364 Mask for fabricating semiconductor components
A mask for fabricating semiconductor components contains first transparent regions and second transparent regions. The second regions are laid out such that they...
US-6,848,617 Smart card module for biometric sensors
In a smart card module for biometric sensors for installation in smart cards, a support has at least one through opening or window in the region of a sensor...
US-6,847,911 Method and apparatus for temperature throttling the access frequency of an integrated circuit
A method of throttling the frequency with which an integrated circuit is accessed includes sensing the temperature of the integrated circuit die and converting...
US-6,847,855 Method for fault analysis in wafer production
With the aid of the method for fault analysis according to the invention, a wide variety of chips are mapped by means of a transformation onto at least one...
US-6,847,812 Frequency-stabilized transceiver configuration
A transceiver configuration has an integrated circuit (IC) with an A/D and/or D/A converter, a VCO with a reference oscillator, which provides a sampling clock...
US-6,847,811 Receiver circuit compensation for filter response error
A circuit configuration having a filter, for example a bandpass filter, and a method for its operation are specified, which the circuit configuration allows for...
US-6,847,669 Sheet-like electrooptical component, light-guide configuration for serial, bidirectional signal transmission...
A flat or sheet-like electrooptical component for sending and receiving electrical and optical signals includes a central emission region with at least one...
US-6,847,643 Scalable data network, and router for a scalable data network
A network comprises routers, wherein at least some of the routers are configured to receive a number of datastreams and to output an aggregated datastream....
US-6,847,581 Integrated circuit and method for operating the integrated circuit
An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first...
US-6,847,571 Use of redundant memory cells to manufacture cost efficient drams with reduced self refresh current capability
A redundant sense amplifier is provided together with a corresponding bit line, which is connected to all word lines in the memory array. This redundant bit line...
US-6,847,568 Sense amplifier configuration for a semiconductor memory device
A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds...
US-6,847,566 Method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device
Methods and circuit configurations for multiple recycling of charge during a refresh operation in a memory device, such as a dynamic random access memory (DRAM)...
US-6,847,410 Picture data memory device with picture data input channels and picture data output channels
A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input...
US-6,847,225 CML (current mode logic) OCD (off chip driver)--ODT (on die termination) circuit for bidirectional data...
An apparatus for use as both an off chip driver (OCD) and an on die termination (ODT) circuits. A preferred embodiment comprises a control circuit (for example,...
US-6,847,092 Microelectronic capacitor structure with radial current flow
A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The...
US-6,847,091 Vertical semiconductor component having a reduced electrical surface field
A vertical semiconductor component having a semiconductor body of a first conductivity type is described. In a surface region of the semiconductor body, at least...
US-6,847,072 Low switching field magnetic element
A magnetic element which can switch states using a relatively lower magnetic field. The magnetic element comprises first and second magnetic layers separated by...
US-6,846,683 Method of forming surface-smoothing layer for semiconductor devices with magnetic material layers
A semiconductor device (118) and method of fabrication thereof, wherein a plurality of conductive lines (124) are formed over a workpiece, a surface-smoothing...
US-6,845,554 Method for connection of circuit units
The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film...
US-6,845,493 Electrical line end shortening quantification
The present invention enables the quantification of line end shortening by utilizing a pattern of multiple conductive paths, each conductive path can include a...
US-6,845,478 Method and apparatus for collecting and displaying bit-fail-map information
Disclosed is a method of testing memory, comprising providing one or more semiconductor wafers having one or more semiconductor chips thereon, each said chip...
US-6,845,252 Programmable echo cancellation filter
Programmable echo cancellation filter for echo signal cancellation for a transceiver having a signal input (13) for receiving the transmission signal emitted by...
US-6,845,048 System and method for monitoring internal voltages on an integrated circuit
A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing...
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