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Patent # Description
US-6,898,747 Method for testing circuit units to be tested with increased data compression for burn-in
The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals...
US-6,898,739 Method and device for testing a memory circuit
A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the...
US-6,898,546 METHOD FOR PROCESSING DATA REPRESENTING PARAMETERS RELATING TO A PLURALITY OF COMPONENTS OF AN ELECTRICAL...
A method for processing first data representing parameters relating to several components of an electrical circuit provides an associated first data record for...
US-6,898,106 Using FeRam/MRAM cells having a high degree of flexibility and compact construction and method of operating the...
A memory device is configured to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate line device of the memory...
US-6,898,104 Semiconductor device having semiconductor memory with sense amplifier
A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense...
US-6,897,993 Electroabsorption modulator, modulator laser device and method for producing an electroabsorption modulator
Electroabsorption modulator (100) having a layer sequence of at least five sequential layers, having at least one light absorption layer (106) which is arranged...
US-6,897,943 Method and apparatus for aerial image improvement in projection lithography using a phase shifting aperture
A plate 50 for projection lithography comprising a first opaque region 54 located at the center of the plate 50 and a second opaque region 56 formed at the outer...
US-6,897,796 Sigma-delta converter arrangement
The invention discloses a sigma-delta converter arrangement with a forward path including an amplifier and a quantizer with a clock input, and a feedback path...
US-6,897,719 Demodulation circuit and demodulation method
Two capacitors are provided for demodulating an amplitude-modulated signal and can be supplied with a signal that is rectified by a diode and that is at a...
US-6,897,646 Method for testing wafers to be tested and calibration apparatus
The invention provides a method for testing wafers (101) to be tested in a test device (100), in which the test device (100) can be calibrated, at least one...
US-6,897,568 Electronic component with flexible contacting pads and method for producing the electronic component
An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material...
US-6,897,517 Multibit non-volatile memory and method
A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby...
US-6,897,501 Avoiding shorting in capacitors
A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is...
US-6,897,485 Device for optical and/or electrical data transmission and/or processing
A device for optical and/or electrical data transmission and/or processing has at least one electrical component, at least one optoelectronic component...
US-6,897,422 Measuring configuration and method for measuring a critical dimension of at least one feature on a...
A scanning electron microscope is integrated in a common measuring configuration with at least one device for the angle-dependent measuring of the scattering or...
US-6,897,112 Method for fabricating an integrated semiconductor configuration with the aid of thermal oxidation, related...
A method for fabricating an integrated semiconductor configuration includes generating a polycrystalline layer at a surface of a base layer and doping the...
US-6,897,107 Method for forming TTO nitride liner for improved collar protection and TTO reliability
A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the...
US-6,897,101 Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory
An integrated magnetoresisitive semiconductor memory configuration has MRAM memory cells located at crossover points of selection lines that are embedded in...
US-6,897,088 Method for connecting circuit devices
A method of connecting a first and second circuit device includes providing a first circuit device having a first main area and a second circuit device having a...
US-6,897,077 Test structure for determining a short circuit between trench capacitors in a memory cell array
A test structure allows determining a short circuit between trench capacitors in a memory cell array in which the trench capacitors are arranged in matrix form....
US-6,896,999 Method of exposing a semiconductor wafer in an exposer
A method for exposing a semiconductor wafer in an exposer includes applying a first resist layer on a layer covering an alignment mark. A microscope measuring...
US-6,896,534 Zero insertion force mount for fixing and making contact with circuit subassemblies on a substrate
A zero insertion force mount for fixing and making contact with circuit subassemblies on a substrate has a plurality of holding devices for holding the circuit...
US-6,895,731 Apparatus for populating transport tapes
An apparatus and a method for populating transport tapes with electronic components includes a mold support having at least one recess over which a flat plastic...
US-6,895,538 Method for testing a device and a test configuration including a device with a test memory
A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a...
US-6,895,294 Assembly comprising a plurality of mask containers, manufacturing system for manufacturing semiconductor...
The present invention relates to a system for the manufacture of semiconductor devices by lithography, and in particular to an assembly of mask containers for...
US-6,895,036 Apparatus and method for sub-chip offset correlation in spread-spectrum communication systems
An embodiment of the present invention described in the specification and the drawings is an apparatus and method for code correlation in spread spectrum...
US-6,894,933 Buffer amplifier architecture for semiconductor memory circuits
A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory...
US-6,894,525 Method and device for time measurement on semiconductor modules employing the ball-grid-array technique
A method and a device for time measurement at a designated signal pin or associated solder pad on a semiconductor module on which semiconductor chips are mounted...
US-6,894,421 Circuit configuration and, in particular, a switch-mode power supply
A circuit configuration, in particular, a switch-mode power supply, includes a transformer device and at least one semiconductor component to provide a...
US-6,894,381 Electronic device having a stack of semiconductor chips and method for the production thereof
The invention relates to an electronic device having a stack of semiconductor chips, and to a method for the production thereof. A first semiconductor chip is...
US-6,894,379 Sharing of multiple-access signal line in a printed circuit board
A printed circuit board system includes a printed circuit board device having a multiple access signal line. A plurality of semiconductor apparatuses are...
US-6,894,378 Electronic component with stacked semiconductor chips
An electronic component with at least two stacked semiconductor chips is described. The chips are respectively mounted on a wiring board. The wiring boards are...
US-6,894,367 Vertical bipolar transistor
A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown...
US-6,894,336 Vertical access transistor with curved channel
An access transistor (140) for a vertical DRAM device (110) and method of forming thereof. Trenches (114) are formed in a semiconductor wafer substrate (112),...
US-6,894,330 Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor
The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory...
US-6,894,329 High-voltage semiconductor component
A semiconductor component has a semiconductor body comprising blocking pn junction, a source zone of a first conductivity type connected to a first electrode and...
US-6,893,972 Process for sidewall amplification of resist structures and for the production of structures having reduced...
The novel process lends itself to the production of highly resolved resist structures. A resist structure having webs is produced from a photoresist on a...
US-6,893,968 Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices
A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process...
US-6,893,959 Method to form selective cap layers on metal features with narrow spaces
Interconnect layers on a semiconductor device containing logic circuits (microprocessors, Asics of others) or random access memory cells (DRAM's) are formed in a...
US-6,893,938 STI formation for vertical and planar transistors
A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask...
US-6,893,935 Semiconductor component and fabrication method
A thin lower electrode layer having an optimally protected capacitor dielectric is produced and structured. A conventional metallization layer for strip...
US-6,893,911 Process integration for integrated circuits
A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a...
US-6,892,937 Method and configuration for operating a multistage counter in one counting direction
A method for operating a multistage counter in only one counting direction is described. The counting value of a single-stage auxiliary counter that can be...
US-6,892,364 Method of analyzing an integrated electric circuit, computer program utilizing the method, data carrier...
An integrated electric circuit includes one or more circuit networks each having a large number of circuit elements. Images of circuit networks are produced on a...
US-6,892,344 Viterbi equalizer using various hardware data paths for ACS and transmission metric operations
A Viterbi equalizer includes a digital signal processor with has a first and a second associated hardware data path. The first data path is intended for carrying...
US-6,892,108 Method for adjusting processing parameters of at least one plate-shaped object in a processing tool
Processing parameters of at least one plate-shaped object, e.g. a semiconductor device or wafer, or a flat panel display, in a processing tool are adjusted...
US-6,892,061 Mixer circuit configuration
A circuit configuration for mixing a differential desired signal with a differential local oscillator signal includes two difference amplifiers which are...
US-6,891,915 Calculating circuit for dividing a fixed-point signal
1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor...
US-6,891,901 Data transmission device
An output signal to be transmitted via an especially two wire transmission line (A, B), which is composed of a transmission signal and a DC supply voltage, is...
US-6,891,886 Apparatus for finely synchronizing code signals
An apparatus for finely synchronizing code signals with an encoded received signal includes a sampling device for sampling the received signal at regular...
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