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Patent # Description
US-6,859,873 Variable length instruction pipeline
A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline...
US-6,859,489 Method and device for determining the carrier frequency of base stations in the mobile receiver of a cellular...
The method and device enable determining the carrier frequency of base stations in the mobile receiver of a cellular mobile radio system working with W-CDMA. The...
US-6,859,411 Circuit and method for writing and reading data from a dynamic memory circuit
A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit...
US-6,859,407 Memory with auto refresh to designated banks
A memory comprising 2.sup.n dynamic random access memory (DRAM) banks, wherein n is an integer greater than or equal to 2, 2.sup.n refresh row address counter...
US-6,859,406 Dynamic RAM semiconductor memory and method for operating the memory
A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are...
US-6,859,398 Semiconductor memory component
A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a...
US-6,859,153 Method and apparatus for changing the rate of time-discrete signals
Methods and apparatus are provided for changing the rate of time-discrete signals. When changing the rate or for the interpolation of time-discrete input values...
US-6,859,011 Method for controlling the charging and discharging phases of a backup capacitor and a circuit configuration...
A method for controlling the charging and discharging phases of a backup capacitor for a data storage medium has the step where the backup capacitor is first...
US-6,858,895 Circuit configuration having a field-effect transistor operable at higher frequencies
A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second...
US-6,858,890 Ferroelectric memory integrated circuit with improved reliability
An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is...
US-6,858,799 Electronic component with a semiconductor chip and method of producing the electronic component
An electronic component includes a semiconductor chip that has an active upper side with integrated circuits and a passive rear side. The rear side and the side...
US-6,858,492 Method for fabricating a semiconductor memory device
Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration...
US-6,858,449 Process and device for the abrasive machining of surfaces, in particular semiconductor wafers
A process for abrasive machining of surfaces of semiconductor wafers, in particular during the production of electronic memory elements, is described. In the...
US-6,858,447 Method for testing semiconductor chips
A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is...
US-6,858,445 Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an...
The present invention provides a method for optimizing the overlay adjustment of two mask planes in a photolithographic process for the production of an...
US-6,858,442 Ferroelectric memory integrated circuit with improved reliability
A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion...
US-6,858,441 MRAM MTJ stack to conductive line alignment method
A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a...
US-6,858,376 Process for structuring a photoresist layer on a semiconductor substrate
In a negative or positive photoresist layer structured with the aid of the customary lithography technique, the photoresist layer is heated briefly, in the...
US-6,857,841 Vehicle for transporting a semiconductor device carrier to a semiconductor processing tool
A vehicle for transporting semiconductor devices is used for servicing loadports of semiconductor processing tools with device carriers by use of a portal hoist....
US-6,857,791 Optical device assembly with an anti-kink protector and transmitting/receiving module
An optical device assembly includes an optical device. The optical device has an optical fiber led from the device with an anti-kink protector, and also a...
US-6,857,789 Coupling configuration for coupling an optical plug with a plug pin to a mounting tubelet
A coupling configuration enables the coupling of an optical plug with a plug pin to a mounting tubelet wherein at least one optical conductor is arranged in at...
US-6,857,091 Method for operating a TAP controller and corresponding TAP controller
The present invention provides a method for operating a TAP controller having a first input terminal (Etms) for inputting a logic test mode selection signal...
US-6,856,769 Optical transceiver module
An optical transceiver module includes an electro-optical transmission assembly and an electro-optical receiving assembly both mounted on a common printed...
US-6,856,721 Light guide configuration for serial bi-directional signal transmission, optical circuit board, and fabrication...
A light guide configuration for serial bi-directional signal transmission includes an optical signal line for carrying electromagnetic radiation along a main...
US-6,856,684 Device and method for echo compensation in a two-wire full duplex channel transmission method
Method and device for echo compensation with a common-frequency transmission method in duplex mode over a two-wire line, an echo compensation filter which has...
US-6,856,562 Test structure for measuring a junction resistance in a DRAM memory cell array
A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a...
US-6,856,560 Redundancy in series grouped memory architecture
An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory...
US-6,856,554 Memory system
A memory system has a memory controller, a plurality of memory modules and a memory bus connected to the memory controller and branching into a plurality of...
US-6,856,186 Circuit configuration for level boosting, in particular for driving a programmable link
A circuit configuration is provided for level boosting, in particular for driving a link that can be programmed by an energy pulse, which is also referred to as...
US-6,856,161 Sensor array and method for detecting the condition of a transistor in a sensor array
A sensor array is provided including transistors that are coupled together. The transistors are designed as sensors and wherein the sensor array has switching...
US-6,855,630 Method for making contact with a doping region of a semiconductor component
A method makes contact with a doping region formed at a substrate surface of a substrate. An insulating layer is applied on the substrate surface and a contact...
US-6,855,612 Method for fabricating a bipolar transistor
A method for producing bipolar transistors with the aid of selective epitaxy for producing a collector and base. The method includes widening the area of the...
US-6,855,596 Method for manufacturing a trench capacitor having an isolation trench
A method for manufacturing a trench capacitor includes the step of etching a shallow isolation trench in a two-step process flow. During a first etching step, an...
US-6,855,565 Semiconductor device having ferroelectric film and manufacturing method thereof
First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor...
US-6,854,997 Device for unlocking an electronic component that is insertible into a receiving device
An apparatus for unlocking an electronic component to be inserted into a retaining device, in particular, a transceiver, and held in the retaining device by a...
US-6,854,484 Valve for a slurry outlet opening of a chemical mechanical polishing device and chemical mechanical polishing...
A valve for a slurry outlet opening in an installation for chemical mechanical polishing, in particular of semiconductor wafers in DRAM production, includes an...
US-6,854,024 Identification of a peripheral connection state with a universal serial bus
A circuit configuration for a USB peripheral has an integrated circuit, which has two pins for connecting to two data transmission lines of a USB connection. A...
US-6,853,836 Polar loop transmission circuit
A polar loop transmission circuit is proposed wherein a signal to be transmitted and a feedback signal are separated into their polar phase and amplitude...
US-6,853,761 Optoelectronic module
An optoelectronic module has at least two components, which are coupled via an optical waveguide, in a monolothically integrated structure. At least two of the...
US-6,853,665 Photodiode configuration having two photodiodes, a laser diode configuration having the photodiode...
A photodiode configuration having at least two photodiodes is described. Accordingly, the photodiodes are formed in a symmetrical configuration on a common...
US-6,853,657 Method and device for determining the output power of a semiconductor laser diode
The invention relates to a method and device for determining the output power of a semiconductor laser diode being operated with a diode current. A defined...
US-6,853,597 Integrated circuits with parallel self-testing
An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a...
US-6,853,509 Acquisition signal error estimator
A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample...
US-6,853,262 Voltage-controlled oscillator circuit which compensates for supply voltage fluctuations
A voltage-controlled oscillator circuit compensates for supply voltage fluctuations of the oscillator and thus for frequency fluctuations at the oscillator...
US-6,853,249 Gm replica cell utilizing an error amplifier connected to a current mirror
A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference...
US-6,853,233 Level-shifting circuitry having "high" output impedance during disable mode
A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a...
US-6,853,232 Power switching device
A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The...
US-6,853,230 Method and apparatus for producing a clock output signal
An apparatus for producing a clock output signal, having an input for receiving an input signal containing a phase information item; a clock generator for...
US-6,853,229 Circuit for transforming a single ended signal into a differential mode signal
An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter 505) and a...
US-6,853,214 Circuit configuration for controlling load-dependent driver strengths
A circuit configuration has a first driver stage for feeding in an input signal and for outputting an amplified signal. A second driver stage, which is connected...
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