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Bond pad structure comprising tungsten or tungsten compound layer on top of
A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon...
Targeted deposition of nanotubes
A method for targeted deposition of a nanotube on a planar surface includes providing a ram made from elastomeric material and having a relief structure on its...
Semiconductor device identification apparatus
A three-dimensional image of a semiconductor device identification pattern is obtained by measuring the distance of at least one sensor to the surface of the...
Method for calculating the capacity of a layout of an integrated circuit
with the aid of a computer, and...
A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of...
Optimized turbo decoder
A turbo decoder for decoding a data signal transmitted via a disturbed channel has a symbol estimator. The symbol estimator contains a computing device, which,...
Method and device for channel encoding in an information transfer system
To achieve an improved disparate error protection in the transmission of coded symbols of an information stream, the information stream is supplied to a...
Test data generator
Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock...
Multitasking processor system for monitoring interrupt events
In a processor system, different memory means (8), which can in each case comprise a memory stack (9) for the instruction counter, a register (10) for...
Three input variable subfield comparation for fast matching
The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number...
Method and apparatus for performing an interfrequency search
The present invention a system and method are provided for performing an inter-frequency search with reduced loss of link frames in a CDMA system. The CDMA...
Clocked integrated semiconductor circuit and method for operating such a
An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is...
Direct current voltage converter with switching regulator
A direct current voltage converter comprises a unit (BGR) for preparing a reference voltage (Vref), a regulator (OP), a pulse width modulator (Comp, Vsw), a...
Piezoelectric resonator device having detuning layer sequence
A resonator device includes a piezoelectric resonator having a detuning layer sequence arranged on the piezoelectric resonator. The detuning layer sequence...
Electronic interface structures and methods
Electronic component, in particular a chip, which can be electrically bonded by means of a plurality of contacts provided on the component to mating contacts...
Controllable semiconductor switching element that blocks in both directions
The controllable semiconductor switching element blocks in both directions. The semiconductor switching element is formed with a first conduction region and a...
Integrated, tunable capacitor
An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal...
Semiconductor configuration and process for etching a layer of the
semiconductor configuration using a...
To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or...
Method of producing large-area membrane masks by dry etching
Based upon an existing or to be produced multi-layered semiconductor-insulator-semiconductor carrier layer wafer (SOI substrate), irregularity of the etching...
Method for fabricating integrated circuit arrangements, and associated
circuit arrangements, in particular...
The invention relates to a method in which an eclectically nonconductive mask layer is applied to an electrically conductive contact layer which is supported by...
Via density rules
Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a...
Compact semiconductor structure
A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor...
Method of forming shallow trench isolation using deep trench isolation
A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating...
Double gate MOSFET transistor and method for the production thereof
A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed...
Configuration and method for making contact with the back surface of a
A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a...
Address counter for addressing synchronous high-frequency digital circuits,
in particular memory devices
The novel address counter can be used in combination with an existing test unit--serving for testing digital circuits--for addressing synchronous high-frequency...
Memory system with reduced refresh current
The present invention is a random access memory device with reduced refresh current and method for use in the same. The memory device includes a memory array...
Method and test circuit for testing a dynamic memory circuit
Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a...
Voltage down converter for low voltage operation
A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage...
Schottky diode having overcurrent protection and low reverse current
The invention relates to a Schottky diode in which p-doped regions (4, 5) are incorporated in the Schottky contact area. At least one (5) of these regions (4, 5)...
Compensation semiconductor component
A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the...
Line configuration for bit lines for contact-connecting at least one memory
cell, semiconductor component with...
A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory...
Bis-o-aminophenols and processes for producing bis-o-aminophenols
A bis-o-aminophenol has a formula I ##STR1## These bis-o-aminophenols permit the preparation of polybenzoxazoles stabilized at high temperatures. The...
Composition and process for the production of a porous layer using the
Production of a porous layer includes using a composition which includes a first polymer component and a second polymer component, the first polymer component...
Method for aligning and exposing a semiconductor wafer
Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the...
Method for fabricating a trench structure
An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to...
Method producing a contact connection between a semiconductor chip and a
substrate and the contact connection
A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The...
Method for producing a structured layer on a semiconductor substrate
A method for producing a structured layer on a semiconductor substrate includes the steps of creating the layer on the substrate, modifying a surface of the...
Device for preventing or reducing tipping of the head
A description is given of a device for avoiding or limiting the tilting of the head forwards and/or to the side of a passenger sitting in a seat which has a...
Variable length instruction pipeline
A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline...
Method and device for determining the carrier frequency of base stations in
the mobile receiver of a cellular...
The method and device enable determining the carrier frequency of base stations in the mobile receiver of a cellular mobile radio system working with W-CDMA. The...
Circuit and method for writing and reading data from a dynamic memory
A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit...
Memory with auto refresh to designated banks
A memory comprising 2.sup.n dynamic random access memory (DRAM) banks, wherein n is an integer greater than or equal to 2, 2.sup.n refresh row address counter...
Dynamic RAM semiconductor memory and method for operating the memory
A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are...
Semiconductor memory component
A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a...
Method and apparatus for changing the rate of time-discrete signals
Methods and apparatus are provided for changing the rate of time-discrete signals. When changing the rate or for the interpolation of time-discrete input values...
Method for controlling the charging and discharging phases of a backup
capacitor and a circuit configuration...
A method for controlling the charging and discharging phases of a backup capacitor for a data storage medium has the step where the backup capacitor is first...
Circuit configuration having a field-effect transistor operable at higher
A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second...
Ferroelectric memory integrated circuit with improved reliability
An IC with memory cells arranged in a chained architecture is disclosed. The top local interconnect between the top capacitor electrodes and active area is...
Electronic component with a semiconductor chip and method of producing the
An electronic component includes a semiconductor chip that has an active upper side with integrated circuits and a passive rear side. The rear side and the side...
Method for fabricating a semiconductor memory device
Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration...