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Patent # Description
US-6,856,560 Redundancy in series grouped memory architecture
An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory...
US-6,856,554 Memory system
A memory system has a memory controller, a plurality of memory modules and a memory bus connected to the memory controller and branching into a plurality of...
US-6,856,186 Circuit configuration for level boosting, in particular for driving a programmable link
A circuit configuration is provided for level boosting, in particular for driving a link that can be programmed by an energy pulse, which is also referred to as...
US-6,856,161 Sensor array and method for detecting the condition of a transistor in a sensor array
A sensor array is provided including transistors that are coupled together. The transistors are designed as sensors and wherein the sensor array has switching...
US-6,855,630 Method for making contact with a doping region of a semiconductor component
A method makes contact with a doping region formed at a substrate surface of a substrate. An insulating layer is applied on the substrate surface and a contact...
US-6,855,612 Method for fabricating a bipolar transistor
A method for producing bipolar transistors with the aid of selective epitaxy for producing a collector and base. The method includes widening the area of the...
US-6,855,596 Method for manufacturing a trench capacitor having an isolation trench
A method for manufacturing a trench capacitor includes the step of etching a shallow isolation trench in a two-step process flow. During a first etching step, an...
US-6,855,565 Semiconductor device having ferroelectric film and manufacturing method thereof
First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor...
US-6,854,997 Device for unlocking an electronic component that is insertible into a receiving device
An apparatus for unlocking an electronic component to be inserted into a retaining device, in particular, a transceiver, and held in the retaining device by a...
US-6,854,484 Valve for a slurry outlet opening of a chemical mechanical polishing device and chemical mechanical polishing...
A valve for a slurry outlet opening in an installation for chemical mechanical polishing, in particular of semiconductor wafers in DRAM production, includes an...
US-6,854,024 Identification of a peripheral connection state with a universal serial bus
A circuit configuration for a USB peripheral has an integrated circuit, which has two pins for connecting to two data transmission lines of a USB connection. A...
US-6,853,836 Polar loop transmission circuit
A polar loop transmission circuit is proposed wherein a signal to be transmitted and a feedback signal are separated into their polar phase and amplitude...
US-6,853,761 Optoelectronic module
An optoelectronic module has at least two components, which are coupled via an optical waveguide, in a monolothically integrated structure. At least two of the...
US-6,853,665 Photodiode configuration having two photodiodes, a laser diode configuration having the photodiode...
A photodiode configuration having at least two photodiodes is described. Accordingly, the photodiodes are formed in a symmetrical configuration on a common...
US-6,853,657 Method and device for determining the output power of a semiconductor laser diode
The invention relates to a method and device for determining the output power of a semiconductor laser diode being operated with a diode current. A defined...
US-6,853,597 Integrated circuits with parallel self-testing
An integrated circuit having a BIST control unit for testing a plurality of memory banks simultaneously is described. The BIST control unit is coupled to a...
US-6,853,509 Acquisition signal error estimator
A system and method for acquisition signal error estimation is provided which uses one or more past values of the sequence to determine the nearest ideal sample...
US-6,853,262 Voltage-controlled oscillator circuit which compensates for supply voltage fluctuations
A voltage-controlled oscillator circuit compensates for supply voltage fluctuations of the oscillator and thus for frequency fluctuations at the oscillator...
US-6,853,249 Gm replica cell utilizing an error amplifier connected to a current mirror
A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference...
US-6,853,233 Level-shifting circuitry having "high" output impedance during disable mode
A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a...
US-6,853,232 Power switching device
A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The...
US-6,853,230 Method and apparatus for producing a clock output signal
An apparatus for producing a clock output signal, having an input for receiving an input signal containing a phase information item; a clock generator for...
US-6,853,229 Circuit for transforming a single ended signal into a differential mode signal
An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter 505) and a...
US-6,853,214 Circuit configuration for controlling load-dependent driver strengths
A circuit configuration has a first driver stage for feeding in an input signal and for outputting an amplified signal. A second driver stage, which is connected...
US-6,853,206 Method and probe card configuration for testing a plurality of integrated circuits in parallel
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test...
US-6,853,085 Method and device for securing a multi-dimensionally constructed chip stack and chip configuration
A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and...
US-6,853,025 Trench capacitor with buried strap
A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which...
US-6,853,023 Semiconductor memory cell configuration and a method for producing the configuration
A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory...
US-6,853,000 Test structure for determining a doping region of an electrode connection between a trench capacitor and a...
A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a...
US-6,852,931 Configuration having an electronic device electrically connected to a printed circuit board
A configuration and also a method for the configuration in which, the configuration has at least one electronic device with associated contact connections and at...
US-6,852,640 Method for fabricating a hard mask
The method is for producing a hard mask on a substrate, and in particular, on a primary area of a semiconductor substrate. The method includes the following...
US-6,852,639 Etching processing method for a material layer
The present invention provides a processing method that changes the given and unfavorable surface contour of a material layer to a predetermined, more favorable...
US-6,852,638 Selective base etching
A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of ...
US-6,852,628 Method of insulating interconnects, and memory cell array with insulated interconnects
The process is used to electrically insulate adjacent metallic interconnects made from an aluminum-containing alloy, in particular for interconnects which are...
US-6,852,598 Method for the fabrication of a DMOS transistor
A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure,...
US-6,852,585 Semiconductor circuit arrangement and a method for producing same
A semiconductor circuit arrangement includes a circuit element embedded in a semiconductor substrate of a first conductivity type in an integrated manner and is...
US-6,852,567 Method of assembling a semiconductor device package
A method of assembling a semiconductor device package includes first attaching a semiconductor device to a die-pad area of a leadframe. Electrical connections...
US-6,852,473 Anti-reflective coating conformality control
A method for forming an anti-reflective coating on a semiconductor substrate, including providing a first vessel containing an anti-reflective coating component...
US-6,852,240 Method of manufacturing a ferroelectric capacitor configuration
A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms...
US-6,851,598 Electronic component with a semiconductor chip and method for producing the electronic component
An electronic component with at least one semiconductor chip and a wiring layer are described. The wiring layer has elastic contact elements of low mechanical...
US-6,850,451 Zero static power fuse for integrated circuits
A fuse cell with reduced or no static power dissipation is disclosed. The fuse cell utilizes a latch to store the state of the fuse. The use of the latch avoids...
US-6,850,448 Temperature-dependent refresh cycle for DRAM
A circuit for generating a refresh signal for a memory cell, includes a temperature-independent current source, a temperature-independent voltage source, and a...
US-6,850,420 Flat mount with at least one semiconductor chip
The flat mount assembly, or transponder, has at least one semiconductor chip that is connected to an antenna for interchanging data and power with an electronic...
US-6,850,414 Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor...
An electronic printed circuit board has a memory module and a contact strip for insertion into another electronic unit. The memory module has at least nine...
US-6,850,111 Charge pump circuit
A charge pump circuit provides an output voltage greater than a supply voltage of the charge pump circuit. The charge pump circuit has a first and a second...
US-6,850,099 Scalable driver device and related integrated circuit
In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal,...
US-6,849,893 Semiconductor circuit structure and method for fabricating the semiconductor circuit structure
A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching...
US-6,849,496 DRAM with vertical transistor and trench capacitor memory cells and method of fabrication
A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A...
US-6,849,495 Selective silicidation scheme for memory devices
A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide...
US-6,849,465 Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition
A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic...
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