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Patent # Description
US-6,867,657 Relaxation oscillator
The invention relates to an electric circuit for generating a periodic signal comprising: a capacitor device which has a first terminal and a second terminal; a...
US-6,867,597 Method and apparatus for finding a fault in a signal path on a printed circuit board
In the case of the present-day trend of miniaturizing housed electronic devices, there is the problem that the contact spacings between the terminal pins becomes...
US-6,867,492 Radio-frequency power component, radio-frequency power module, method for producing a radio-frequency power...
A radio-frequency power component and a radio-frequency power module, as well as to methods for producing them are encompassed. The radio-frequency power...
US-6,867,479 Method for rewiring pads in a wafer-level package
A method for rewiring contact pads in the wafer-level package is inventively provided. In order to be able to make the terminals of the characterization pads...
US-6,867,472 Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by...
A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the...
US-6,867,471 Universal package for an electronic component with a semiconductor chip and method for producing the universal...
An electronic component has a semiconductor chip with chip contacts. The chip contacts are mechanically fixed on a wiring structure and electrically connected to...
US-6,867,442 Surface-functionalized inorganic semiconductor particles as electrical semiconductors for microelectronics...
A semiconductor device has a first contact, by which charge carriers are injected into a semiconductor path, and a second contact, by which the charge carriers...
US-6,867,137 Fabrication method for a semiconductor structure having a partly filled trench
The present invention provides a fabrication method for a semiconductor structure having a partly filled trench, having the following steps: provision of a...
US-6,867,105 Bipolar transistor and method of fabricating a bipolar transistor
A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third...
US-6,867,087 Formation of dual work function gate electrode
In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate...
US-6,867,053 Fabrication of a FeRAM capacitor using a noble metal hardmask
A ferroelectric capacitor is fabricated using a noble metal hardmask. A hardmask is deposited on a top electrode of a capacitor stack comprising a ferroelectric...
US-6,866,980 Bis-o-aminophenol derivatives, poly-o-hydroxyamides, and polybenzoxazoles, usable in photosensitive...
Bis-o-aminophenols, which carry on at least one of their hydroxyl groups a tert-butoxy-carbonyl group, can be reacted with dicarboxylic acids to give the...
US-6,866,943 Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level
A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon...
US-6,866,891 Targeted deposition of nanotubes
A method for targeted deposition of a nanotube on a planar surface includes providing a ram made from elastomeric material and having a relief structure on its...
US-6,866,200 Semiconductor device identification apparatus
A three-dimensional image of a semiconductor device identification pattern is obtained by measuring the distance of at least one sensor to the surface of the...
US-6,865,727 Method for calculating the capacity of a layout of an integrated circuit with the aid of a computer, and...
A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of...
US-6,865,712 Optimized turbo decoder
A turbo decoder for decoding a data signal transmitted via a disturbed channel has a symbol estimator. The symbol estimator contains a computing device, which,...
US-6,865,709 Method and device for channel encoding in an information transfer system
To achieve an improved disparate error protection in the transmission of coded symbols of an information stream, the information stream is supplied to a...
US-6,865,707 Test data generator
Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock...
US-6,865,636 Multitasking processor system for monitoring interrupt events
In a processor system, different memory means (8), which can in each case comprise a memory stack (9) for the instruction counter, a register (10) for...
US-6,865,590 Three input variable subfield comparation for fast matching
The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number...
US-6,865,173 Method and apparatus for performing an interfrequency search
The present invention a system and method are provided for performing an inter-frequency search with reduced loss of link frames in a CDMA system. The CDMA...
US-6,864,730 Clocked integrated semiconductor circuit and method for operating such a circuit
An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is...
US-6,864,671 Direct current voltage converter with switching regulator
A direct current voltage converter comprises a unit (BGR) for preparing a reference voltage (Vref), a regulator (OP), a pulse width modulator (Comp, Vsw), a...
US-6,864,619 Piezoelectric resonator device having detuning layer sequence
A resonator device includes a piezoelectric resonator having a detuning layer sequence arranged on the piezoelectric resonator. The detuning layer sequence...
US-6,864,575 Electronic interface structures and methods
Electronic component, in particular a chip, which can be electrically bonded by means of a plurality of contacts provided on the component to mating contacts...
US-6,864,535 Controllable semiconductor switching element that blocks in both directions
The controllable semiconductor switching element blocks in both directions. The semiconductor switching element is formed with a first conduction region and a...
US-6,864,528 Integrated, tunable capacitor
An integrated, tunable capacitor has terminal regions that extend significantly deeper into the semiconductor body than the customary source/drain terminal...
US-6,864,188 Semiconductor configuration and process for etching a layer of the semiconductor configuration using a...
To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or...
US-6,864,182 Method of producing large-area membrane masks by dry etching
Based upon an existing or to be produced multi-layered semiconductor-insulator-semiconductor carrier layer wafer (SOI substrate), irregularity of the etching...
US-6,864,175 Method for fabricating integrated circuit arrangements, and associated circuit arrangements, in particular...
The invention relates to a method in which an eclectically nonconductive mask layer is applied to an electrically conductive contact layer which is supported by...
US-6,864,171 Via density rules
Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a...
US-6,864,170 Compact semiconductor structure
A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor...
US-6,864,151 Method of forming shallow trench isolation using deep trench isolation
A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating...
US-6,864,129 Double gate MOSFET transistor and method for the production thereof
A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed...
US-6,863,769 Configuration and method for making contact with the back surface of a semiconductor substrate
A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a...
US-6,862,702 Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices
The novel address counter can be used in combination with an existing test unit--serving for testing digital circuits--for addressing synchronous high-frequency...
US-6,862,238 Memory system with reduced refresh current
The present invention is a random access memory device with reduced refresh current and method for use in the same. The memory device includes a memory array...
US-6,862,234 Method and test circuit for testing a dynamic memory circuit
Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a...
US-6,861,872 Voltage down converter for low voltage operation
A voltage down converter for a semiconductor memory device to convert an external voltage to a lower value internal voltage for the device, has a voltage...
US-6,861,723 Schottky diode having overcurrent protection and low reverse current
The invention relates to a Schottky diode in which p-doped regions (4, 5) are incorporated in the Schottky contact area. At least one (5) of these regions (4, 5)...
US-6,861,706 Compensation semiconductor component
A compensation semiconductor component has a drift zone formed in a semiconductor body and at least one compensation zone formed in the edge region of the...
US-6,861,688 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with...
A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory...
US-6,861,560 Bis-o-aminophenols and processes for producing bis-o-aminophenols
A bis-o-aminophenol has a formula I ##STR1## These bis-o-aminophenols permit the preparation of polybenzoxazoles stabilized at high temperatures. The...
US-6,861,479 Composition and process for the production of a porous layer using the composition
Production of a porous layer includes using a composition which includes a first polymer component and a second polymer component, the first polymer component...
US-6,861,331 Method for aligning and exposing a semiconductor wafer
Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the...
US-6,861,312 Method for fabricating a trench structure
An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to...
US-6,861,291 Method producing a contact connection between a semiconductor chip and a substrate and the contact connection
A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The...
US-6,861,206 Method for producing a structured layer on a semiconductor substrate
A method for producing a structured layer on a semiconductor substrate includes the steps of creating the layer on the substrate, modifying a surface of the...
US-6,860,563 Device for preventing or reducing tipping of the head
A description is given of a device for avoiding or limiting the tilting of the head forwards and/or to the side of a passenger sitting in a seat which has a...
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