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Patent # Description
US-6,891,252 Electronic component with a semiconductor chip and method of producing an electronic component
An electronic component includes a semiconductor chip which has an active upper side and a passive rear side. The semiconductor chip is surrounded by a sawn...
US-6,891,223 Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell
Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the...
US-6,891,204 Semiconductor component having field-shaping regions
A semiconductor element has a semiconductor body of a first conductivity type. The semiconductor body has a zone of a second conductivity type embedded. Further...
US-6,890,833 Trench isolation employing a doped oxide trench fill
A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least...
US-6,890,815 Reduced cap layer erosion for borderless contacts
A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch...
US-6,890,699 Polymer material having a low glass transition temperature for use in chemically amplified photoresists for...
The invention relates to a polymer obtained by copolymerization of a first comonomer having a group catalytically cleavable by acid, a second comonomer having an...
US-6,890,689 Method for fabricating a mask configuration
During the fabrication of a mask, to substantially avoid systematic deviations from a desired configuration of recesses that will be formed in the mask, the...
US-6,889,154 Method and apparatus for calibrating data-dependent noise prediction
Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise...
US-6,888,939 Circuit for joint transmitting voice and data over a telephone line
The invention relates to an SLIC circuit (1), which is connected directly to a telephone line (2), for joint transmission of voice and data via the telephone...
US-6,888,877 CDMA receiver
CDMA Receiver. According to one embodiment, a CDMA receiver is provided for receiving a CDMA signal in a multi-subscriber environment. The multi-subscriber...
US-6,888,767 Dual power sensing scheme for a memory device
Sensing operations involving a first array of bit line sense amplifiers (BLSAs) may be powered by an upper reference voltage and a first intermediate voltage and...
US-6,888,753 Memory cell array comprising individually addressable memory cells and method of making the same
A memory cell array comprises a plurality of memory transistors arranged in a two-dimensional array, each memory transistor having two source/drain regions...
US-6,888,744 Selection device for a semiconductor memory device
A selection device for a semiconductor memory device for preventing voltage drops caused by read currents in a column multiplexer of a semiconductor memory...
US-6,888,430 Integrated radiofrequency circuit component having a trimming diode controlled by a trimming voltage provided...
An integrated component for radiofrequency applications has a resonant circuit with tuning diodes and trimming diodes that are connected in parallel. A...
US-6,888,416 Oscillator/mixer circuit having reduced area requirement when produced on a chip
An oscillator/mixer circuit having a reduced area requirement when producing it on a chip and where the circuit's mixer circuit is not based on the use of the...
US-6,888,407 Multistage differential amplifier with CMFB circuit
The invention relates to a multistage differential amplifier having an input stage, at which a differential input voltage is present, a load connected to the...
US-6,888,365 Semiconductor wafer testing system
A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die...
US-6,888,260 Alignment or overlay marks for semiconductor processing
An alignment or overlay mark with improved signal to noise ratio is disclosed. Improved signal-to-noise ratio results in greater depth of focus, thus improving...
US-6,888,256 Compliant relief wafer level packaging
A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant...
US-6,888,244 Interconnect arrangement and method for fabricating an interconnect arrangement
An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface...
US-6,888,226 Semiconductor structure and method for improving its ability to withstand electrostatic discharge (ESD) and...
A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having...
US-6,888,215 Dual damascene anti-fuse with via before wire
An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive...
US-6,888,211 High-voltage diode
A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity....
US-6,887,783 Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof
An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is...
US-6,887,777 Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
The present invention provides a method for connecting an integrated circuit to a substrate, which has the following steps: provision of a first electrical...
US-6,887,764 Method for producing a gate structure for an MOS transistor
In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a...
US-6,887,761 Vertical semiconductor devices
A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose...
US-6,887,722 Method for exposing a semiconductor wafer
A method for exposing a semiconductor wafer compensates for the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by...
US-6,887,653 Method for structuring a photoresist layer
A method for structuring a photoresist layer is described. A substrate has a photoresist layer containing a film-forming polymer that has a photo acid generator...
US-6,887,437 Reactor configuration and method for producing it
A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into...
US-6,887,358 Installation for processing wafers
An installation for processing wafers with a plurality of fabrication units and a plurality of measurement units as well as a transport system for transporting...
US-6,887,026 Semiconductor product container and system for handling a semiconductor product container
A system for handling a semiconductor product container contains a handler for transporting and positioning the container. A loading/unloading position requires...
US-6,885,963 Method for testing a program-controlled unit by an external test device
A method described is distinguished by the fact that an external test device brings about the execution, in a program-controlled unit, of a program that...
US-6,885,826 Optical transmitter and method for generating a digital optical signal sequence
An optical transmitter and a method for generating a digital optical signal sequence are provided. The optical transmitter has light transmitters which are...
US-6,885,597 Sensing test circuit
A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read...
US-6,885,443 Drive device for a light-emitting component
A drive device for a light emitting component includes a reference source for generating a power stipulation signal that stipulates a desired power. A correction...
US-6,885,254 Calibration device and method for generating a clock in an integrated circuit
To generate an accurate frequency standard in an integrated circuit, it is proposed to activate a reference oscillator at certain time intervals and to calibrate...
US-6,885,220 Current source circuit
A current source circuit is characterized in that it contains a control device that controls a component of the current source circuit that determines a variable...
US-6,885,077 Schottky diode
A Schottky diode has a Schottky junction formed by a thin metal layer and/or metal silicide layer at the top side of a doped well in a semiconductor body or...
US-6,885,062 MOS transistor device with a locally maximum concentration region between the source region and the drain region
In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in...
US-6,884,703 Manufacturing of a low-noise mos device
At the surface of a substrate a gate oxide layer is produced and is given a dual thickness. A first oxide layer is produced over the surface of a substrate by...
US-6,884,688 Method for producing a MOS transistor and MOS transistor
A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain...
US-6,884,676 Vertical 8F2 cell dram with active area self-aligned to bit line
A memory cell is formed in a memory cell array comprised of a plurality of memory cells arranged in rows and columns. A deep trench structure is formed within a...
US-6,884,639 Semiconductor wafer pod
A semiconductor wafer pod includes a measurement sensor configured within a housing. The sensor faces towards a surface of a wafer being accommodated in the pod....
US-6,884,630 Two-step magnetic tunnel junction stack deposition
Magnetic tunnel junction devices can be fabricated using a two-step deposition process wherein respective portions of the magnetic tunnel junction stack are...
US-6,884,567 Photosensitive formulation for buffer coatings, film containing the photosensitive formulation, and method for...
A photosensitive formulation for high-temperature-resistant photoresists is based on polyhydroxyamides. The photosensitive formulations display a much higher...
US-6,883,381 Acceleration sensor and method for manufacturing an acceleration sensor
An acceleration sensor includes a deflectable pressure measuring diaphragm and a counter-structure, which is deflectable as against the pressure measuring...
US-6,882,633 Method and device for synchronizing a mobile radio receiver with a frame structure of a radio signal
A method for synchronizing a mobile radio receiver with a frame structure of a radio signal received from a specific base station assumes that each base station...
US-6,882,584 Method for operating a semiconductor memory, and semiconductor memory
A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of...
US-6,882,556 Semiconductor memory having a configuration of memory cells
A semiconductor memory has a novel geometry of a memory cell array. Without reducing the distance between storage capacitors that are the most closely adjacent...
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