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Patent # Description
US-6,922,073 Circuit configuration for signal balancing in antiphase bus drivers
A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier...
US-6,921,691 Transistor with dopant-bearing metal in source and drain
A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are...
US-6,920,582 Method and apparatus for testing circuit modules
A method and apparatus for testing by sampling vectors circuit modules designated as channel models or as control modules and containing scan chains. Use is made...
US-6,920,523 Bank address mapping according to bank retention time in dynamic random access memories
A system and method for refreshing data in a dynamic random access memory ("DRAM") is provided, where the system includes a data memory having a plurality of...
US-6,920,473 Method and apparatus for modular multiplying and calculating unit for modular multiplying
A multiplicand is multiplied by a multiplier using a modulus. The multiplicand, the multiplier and the modulus are polynomials of variable. A multiplication...
US-6,920,342 Electronic device having an operating mode and an energy saving standby mode, and a method for switching...
An electronic device has an operating mode and an energy saving standby mode. The electronic device includes an input-side antenna element for receiving a signal...
US-6,920,336 Broadband driver
Broadband driver for signals that are transmitted in different frequency ranges, comprising: (a) a first broadband driver circuit (19) for driving first signals...
US-6,920,074 Method for reading a memory cell in a semiconductor memory, and semiconductor memory
In a semiconductor memory, there is capacitive coupling between bit lines that largely run in parallel. Outer sections of the bit lines are connected via...
US-6,920,059 Reducing effects of noise coupling in integrated circuits with memory arrays
A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines,...
US-6,919,767 Circuit arrangement for low-noise fully differential amplification
The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the...
US-6,919,755 Voltage regulator
The invention relates to a voltage regulating circuit arrangement for converting a first voltage (VEXT) applied to an input of said voltage regulating circuit...
US-6,919,618 Shielding device for integrated circuits
A shielding device includes optical and/or electrical shielding disposed on the side of the integrated circuit in the semiconductor chip facing the substrate....
US-6,919,269 Production method for a semiconductor component
A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon...
US-6,919,264 Method for the solder-stop structuring of elevations on wafers
A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps,...
US-6,919,255 Semiconductor trench structure
A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal...
US-6,919,234 Method for producing an antifuse in a substrate and an antifuse structure for integration in a substrate
Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the...
US-6,919,232 Process for producing a semiconductor chip
A process for producing a semiconductor chip having contact elements protruding on one chip side within the context of wafer level packaging, the chip side...
US-6,919,147 Production method for a halftone phase mask
The present invention provides a production method for a halftone phase mask which has an SiO.sub.2 substrate, an overlying refractory metal Si.sub.x N.sub.y...
US-6,918,778 Configuration, plug-in mount and contact element for fixing and contacting switching assemblies on a substrate
Contact elements of a plug-in mount are connected in an electrically conducting manner to conductive contact zones on a surface of a substrate after the plug-in...
US-6,918,535 Security paper, method and device for checking the authenticity of documents recorded thereon
A safety paper with an embedded electronic circuit (1, 4, 7) is used to create more effective forgery-proof securities such as bank notes. In order to check...
US-6,917,563 Integrated memory
An integrated memory contains an access controller for controlling an access for the purpose of reading data from, or writing data to, a memory cell array. The...
US-6,917,562 Semi-conductor component with clock relaying device
The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK,...
US-6,917,549 Integrated memory and method for operating it
An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs...
US-6,917,234 Power switch arrangement and turn-off method therefor
The invention relates to a power switch arrangement having a semiconductor power switch connected by its load path serially in a load circuit, and a clamping...
US-6,917,214 Method for testing a plurality of devices disposed on a wafer and connected by a common data line
In a method for testing a plurality of devices, which are arranged on a wafer and connected to a common data line, wherein the devices are connectable to a test...
US-6,917,208 Method and test structure for determining resistances at a plurality of interconnected resistors in an...
A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are...
US-6,917,100 Circuit module having interleaved groups of circuit chips
A circuit module has a carrier (10) and multiple stacks of circuit chips arranged on a surface of the carrier. Each stack has multiple circuit chips arranged in...
US-6,917,055 Optoelectronic component and method for producing an optoelectronic component
An optoelectronic component has at least one light source which is monolithically integrated in a semiconductor material, in particular having a laser diode. At...
US-6,916,729 Salicide formation method
A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a...
US-6,916,721 Method for fabricating a trench capacitor with an insulation collar
A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried...
US-6,916,704 Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor
An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being...
US-6,916,185 Connection of integrated circuit to a substrate
The present invention provides a method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. Connecting occurs by...
US-6,915,945 Method for contact-connecting an electrical component to a substrate having a conductor structure
For the purpose of contact-connecting an electrical component, in particular a semiconductor component, on a substrate having a conductor structure, a joining...
US-6,914,851 Circuit element with timing control
A circuit element has an input for receiving an external clock with a clock period duration. A unit is provided to present the circuit element with information...
US-6,914,844 Deep power down switch for memory device
A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor...
US-6,914,841 System and method for refreshing a dynamic memory device
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a...
US-6,914,837 DRAM memory with a shared sense amplifier structure
A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as...
US-6,914,834 System and method for the functional testing of semiconductor memory chips
A system and a method for functionally testing fast semiconductor memory chips. The data shifting method proposed here is based on the fact that a low speed...
US-6,914,811 Method of driving one-time operable isolation elements and circuit for driving the isolation elements
A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation...
US-6,914,796 Semiconductor memory element with direct connection of the I/Os to the array logic
The invention relates to a semiconductor memory element comprising a plurality of data pins and at least two memory cell arrays, each of which comprises a...
US-6,914,491 Controlling an oscillator or a phase-delay device in a phase-control circuit
In a phase control loop, an output signal which is used to control an oscillator in a PLL or a phase-delay device in a DLL is generated by means of a...
US-6,914,328 Electronic component with an insulating layer formed from fluorinated norbornene polymer and method for...
An electronic component and a method of producing it, with at least one insulating layer is encompassed by the invention. The insulating layer includes a polymer...
US-6,914,320 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof
An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is...
US-6,914,297 Configuration for generating a voltage sense signal in a power semiconductor component
The invention relates to a configuration for generating a low-voltage signal proportional to the high voltage present between the source and the drain of a power...
US-6,914,292 Floating gate field-effect transistor
A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically...
US-6,914,270 IGBT with PN insulation and production method
The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same...
US-6,913,990 Method of forming isolation dummy fill structures
A method of providing dummy fill structures to meet the strict requirements for planarizing MRAM (Magnetic Random Access Memory) and other semiconductor devices...
US-6,913,987 Method for fabricating self-aligned contact connections on buried bit lines
Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word...
US-6,913,983 Integrated circuit arrangement and method for the manufacture thereof
A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the...
US-6,913,954 Programmable fuse device
A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first...
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