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Patent # Description
US-6,907,544 Method for operating memory devices for storing data
A storage device is disclosed and is characterized in that the data to be stored therein can be automatically and repeatedly stored in the device and/or in that...
US-6,906,972 Integrated DRAM semiconductor memory and method for operating the same
An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the...
US-6,906,969 Hybrid fuses for redundancy
A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical...
US-6,906,942 Programmable mask ROM building element and process of manufacture
A semiconductor memory component such as a mask-programmable ROM component, has two memory cell transistors adjacent to each other in one column of a memory cell...
US-6,906,928 Electronic component with a semiconductor chip, and method of producing the electronic component
The electronic component has a semiconductor chip mounted to a wiring board. The chip is bonded to the wiring board with adhesive strips that leave free a...
US-6,906,908 Semiconductor device and method of manufacturing the same
Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which...
US-6,906,904 Integrated, tunable capacitance
An integrated, tunable capacitance is specified in which the quality factor is improved by virtue of the fact that, instead of source/drain regions, provision is...
US-6,906,569 Digital signal delay device
The invention relates to a digital signal delay device (101) for converting a signal (IN) into a corresponding delayed signal (OUT), comprising a plurality of...
US-6,906,514 Concept for compensating the influences of external disturbing quantities on physical functional parameters of...
A circuit for generating an output signal, which depends on a physical useful quantity includes means for detecting the physical useful quantity, wherein the...
US-6,906,428 Electronic component having a semiconductor chip and method for populating a circuit carrier during the...
An electronic component and a method for populating a circuit carrier during the production of the electronic component includes providing the semiconductor chip...
US-6,906,371 Wordline gate contact for an MBIT transistor array layout
A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored...
US-6,906,370 Semiconductor component having a material reinforced contact area
A semiconductor component having a material-reinforced contact area formed of a metal layer is disclosed. The contact area is jointly formed by a second metal...
US-6,905,954 Method for producing a semiconductor device and corresponding semiconductor device
The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level (11, 12) to a semiconductor...
US-6,905,944 Sacrificial collar method for improved deep trench processing
A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion...
US-6,905,916 Method for processing a surface of an SiC semiconductor layer and Schottky contact
A method for treating a surface on an SiC semiconductor body produced by epitaxy. According to the method, the parts of the epitactic layer that are deposited in...
US-6,905,892 Operating method for a semiconductor component
The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the...
US-6,905,726 Component having at least two mutually adjacent insulating layers and corresponding production method
The invention relates to a component having two adjacent insulating layers and to a production process therefore. The component has an activated insulating...
US-6,904,472 Receiving device for receiving data
A description is given of a receiving device for receiving data. The receiving device extracts from the received data a specific part thereof and, depending on...
US-6,904,445 Method and device for calculating a discrete orthogonal transformation such as FFT or IFFT
The invention comprises a method for calculating an orthogonal discrete transform on the basis of the DIT method in prescribed intermediate steps with the...
US-6,904,039 Packet queuing for a network switch
According to one embodiment a network switch is disclosed. The switch includes a first media access controller (MAC) coupled to a plurality of ports and a memory...
US-6,903,982 Bit line segmenting in random access memories
An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a...
US-6,903,959 Sensing of memory integrated circuits
A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for...
US-6,903,932 Covering element for subassemblies
A covering element for covering subassemblies having a substrate and at least one component disposed thereon and to be protected, in particular, a semiconductor...
US-6,903,620 Circuit configuration for setting the input resistance and the input capacitance of an integrated semiconductor...
An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip....
US-6,903,565 Apparatus and method for the parallel and independent testing of voltage-supplied semiconductor devices
An apparatus for the parallel and independent testing of a plurality of semiconductor devices disposed on a wafer, in which the semiconductor devices are in each...
US-6,903,454 Contact spring configuration for contacting a semiconductor wafer and method for producing a contact spring...
A contact spring configuration for contacting semiconductor wafers is provided. At least one strip-type contact spring is provided on a substrate. The contact...
US-6,903,430 Digital magnetic memory cell device
A digital magnetic memory cell device for read and/or write operations has a soft-magnetic read and/or write layer system formed of at least one soft-magnetic...
US-6,903,423 Integrated semiconductor memory and method for reducing leakage currents in an integrated semiconductor
An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block...
US-6,903,416 Trench transistors and methods for fabricating trench transistors
A trench transistor has a source zone introduced from a doped spacer into a body region and a channel running vertically along the insulation layer of the...
US-6,903,326 OPTO-electronic assembly having detectors for converting optical signals
The opto-electronic assembly receiving optical signals. Two detectors, each with an optically active area, convert optical signals into electrical signals. Two...
US-6,903,009 Methods for fabricating a contact for an integrated circuit
According to one embodiment, a method for fabricating a contact is provided. The method can include a step of depositing a Ti layer in order to completely fill a...
US-6,902,951 Electronic device configured as a multichip module, leadframe, panel with leadframe positions, and method for...
An electronic device has, as a multichip module, two or more semiconductor chips that are integrated into a leadframe such that a placement side of the leadframe...
US-6,902,854 Method for carrying out a rule-based optical proximity correction with simultaneous scatter bar insertion
Lithographic fabrication of a microelectronic component is performed with the aid of OPC and a scatter bar structure. At least one scatter bar in applied on a...
US-6,902,100 Method of improving the quality of soldered connections
The invention relates to a method for improving the quality of soldered connections between large-area SMD components and wiring carriers, in the case of which...
US-6,901,091 Electronic driver circuit for directly modulated semiconductor lasers
An electronic driver circuit for a directly modulated semiconductor laser has a first circuit for generating a constant current and second circuit for modulating...
US-6,900,626 Voltage generator arrangement
A voltage generator arrangement supplies a largely constant output voltage with a high current driver capability. A bandgap reference circuit is downstream from...
US-6,900,516 Semiconductor fuse device
An increased number of fuses per area are provided in this semiconductor device while complying with the predetermined distance between the fuses. The device...
US-6,900,495 Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement
The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has...
US-6,900,284 POLY-O-HYDROXYAMIDES, POLYBENZOXAZOLES, PROCESSES FOR PRODUCING POLY-O-HYDROXYAMIDES, PROCESSES FOR PRODUCING...
Poly-o-hydroxyamides are cyclicized to obtain polybenzoxazoles. The poly-o-hydroxyamides provide effective filling of trenches. In particular, the...
US-6,900,130 Method for locally heating a region in a semiconductor substrate
A method is proposed for locally heating a region that is disposed in a substrate. A substrate is provided and at least one region is produced in the substrate...
US-6,899,997 Process for modifying resist structures and resist films from the aqueous phase
A process for chemically amplifying structured resists includes applying a chemically amplified resist to a substrate and structuring it in a customary manner....
US-6,899,597 Chemical mechanical polishing (CMP) process using fixed abrasive pads
A semiconductive wafer having a layer of conductive material formed thereon is polished. The semiconductor wafer is rotated against an abrasive polishing pad. A...
US-6,899,543 Test structure for determining the electrical loadability of contacts
A test structure can be used to determine the electrical loadability of contacts. This structure includes a first interconnect line and a second interconnect...
US-6,898,747 Method for testing circuit units to be tested with increased data compression for burn-in
The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals...
US-6,898,739 Method and device for testing a memory circuit
A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the...
US-6,898,546 METHOD FOR PROCESSING DATA REPRESENTING PARAMETERS RELATING TO A PLURALITY OF COMPONENTS OF AN ELECTRICAL...
A method for processing first data representing parameters relating to several components of an electrical circuit provides an associated first data record for...
US-6,898,106 Using FeRam/MRAM cells having a high degree of flexibility and compact construction and method of operating the...
A memory device is configured to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate line device of the memory...
US-6,898,104 Semiconductor device having semiconductor memory with sense amplifier
A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense...
US-6,897,993 Electroabsorption modulator, modulator laser device and method for producing an electroabsorption modulator
Electroabsorption modulator (100) having a layer sequence of at least five sequential layers, having at least one light absorption layer (106) which is arranged...
US-6,897,943 Method and apparatus for aerial image improvement in projection lithography using a phase shifting aperture
A plate 50 for projection lithography comprising a first opaque region 54 located at the center of the plate 50 and a second opaque region 56 formed at the outer...
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