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Circuit configuration and, in particular, a switch-mode power supply
A circuit configuration, in particular, a switch-mode power supply, includes a transformer device and at least one semiconductor component to provide a...
Electronic device having a stack of semiconductor chips and method for the
The invention relates to an electronic device having a stack of semiconductor chips, and to a method for the production thereof. A first semiconductor chip is...
Sharing of multiple-access signal line in a printed circuit board
A printed circuit board system includes a printed circuit board device having a multiple access signal line. A plurality of semiconductor apparatuses are...
Electronic component with stacked semiconductor chips
An electronic component with at least two stacked semiconductor chips is described. The chips are respectively mounted on a wiring board. The wiring boards are...
Vertical bipolar transistor
A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown...
Vertical access transistor with curved channel
An access transistor (140) for a vertical DRAM device (110) and method of forming thereof. Trenches (114) are formed in a semiconductor wafer substrate (112),...
Memory configuration and method for reading a state from and storing a
state in a ferroelectric transistor
The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory...
High-voltage semiconductor component
A semiconductor component has a semiconductor body comprising blocking pn junction, a source zone of a first conductivity type connected to a first electrode and...
Process for sidewall amplification of resist structures and for the
production of structures having reduced...
The novel process lends itself to the production of highly resolved resist structures. A resist structure having webs is produced from a photoresist on a...
Defect-minimizing, topology-independent planarization of process surfaces
in semiconductor devices
A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process...
Method to form selective cap layers on metal features with narrow spaces
Interconnect layers on a semiconductor device containing logic circuits (microprocessors, Asics of others) or random access memory cells (DRAM's) are formed in a...
STI formation for vertical and planar transistors
A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask...
Semiconductor component and fabrication method
A thin lower electrode layer having an optimally protected capacitor dielectric is produced and structured. A conventional metallization layer for strip...
Process integration for integrated circuits
A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a...
Method and configuration for operating a multistage counter in one counting
A method for operating a multistage counter in only one counting direction is described. The counting value of a single-stage auxiliary counter that can be...
Method of analyzing an integrated electric circuit, computer program
utilizing the method, data carrier...
An integrated electric circuit includes one or more circuit networks each having a large number of circuit elements. Images of circuit networks are produced on a...
Viterbi equalizer using various hardware data paths for ACS and
transmission metric operations
A Viterbi equalizer includes a digital signal processor with has a first and a second associated hardware data path. The first data path is intended for carrying...
Method for adjusting processing parameters of at least one plate-shaped
object in a processing tool
Processing parameters of at least one plate-shaped object, e.g. a semiconductor device or wafer, or a flat panel display, in a processing tool are adjusted...
Mixer circuit configuration
A circuit configuration for mixing a differential desired signal with a differential local oscillator signal includes two difference amplifiers which are...
Calculating circuit for dividing a fixed-point signal
1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor...
Data transmission device
An output signal to be transmitted via an especially two wire transmission line (A, B), which is composed of a transmission signal and a DC supply voltage, is...
Apparatus for finely synchronizing code signals
An apparatus for finely synchronizing code signals with an encoded received signal includes a sampling device for sampling the received signal at regular...
Input buffer with differential amplifier
Embodiments of the present invention are illustrated in a random access memory. In one embodiment, a random access memory comprises an array of memory cells, a...
Buffer memory device
A buffer memory device buffer-stores data that are to be forwarded. The assembly contains a monitoring device, which monitors the outputting of data requested...
Charge trapping memory cell, method for fabricating it, and semiconductor
For particularly flexible and space-saving information storage, a charge trapping memory cell and a corresponding semiconductor memory device include a charge...
Element storage layer in integrated circuits
Reduced degradation to capacitor properties is disclosed. A hydrogen storage layer is provided over at least a portion a top capacitor electrode. The hydrogen...
Integrated semiconductor circuit configuration
To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line...
Auto-adjustment of self-refresh frequency
A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the...
A semiconductor component has at least one Peltier element and at least one thermogenerator element that are thermally coupled to one another via a coupling...
Electronic component with a semiconductor chip and method of producing an
An electronic component includes a semiconductor chip which has an active upper side and a passive rear side. The semiconductor chip is surrounded by a sawn...
Transistor configuration with a structure for making electrical contact
with electrodes of a trench transistor cell
Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the...
Semiconductor component having field-shaping regions
A semiconductor element has a semiconductor body of a first conductivity type. The semiconductor body has a zone of a second conductivity type embedded. Further...
Trench isolation employing a doped oxide trench fill
A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least...
Reduced cap layer erosion for borderless contacts
A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch...
Polymer material having a low glass transition temperature for use in
chemically amplified photoresists for...
The invention relates to a polymer obtained by copolymerization of a first comonomer having a group catalytically cleavable by acid, a second comonomer having an...
Method for fabricating a mask configuration
During the fabrication of a mask, to substantially avoid systematic deviations from a desired configuration of recesses that will be formed in the mask, the...
Method and apparatus for calibrating data-dependent noise prediction
Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise...
Circuit for joint transmitting voice and data over a telephone line
The invention relates to an SLIC circuit (1), which is connected directly to a telephone line (2), for joint transmission of voice and data via the telephone...
CDMA Receiver. According to one embodiment, a CDMA receiver is provided for receiving a CDMA signal in a multi-subscriber environment. The multi-subscriber...
Dual power sensing scheme for a memory device
Sensing operations involving a first array of bit line sense amplifiers (BLSAs) may be powered by an upper reference voltage and a first intermediate voltage and...
Memory cell array comprising individually addressable memory cells and
method of making the same
A memory cell array comprises a plurality of memory transistors arranged in a two-dimensional array, each memory transistor having two source/drain regions...
Selection device for a semiconductor memory device
A selection device for a semiconductor memory device for preventing voltage drops caused by read currents in a column multiplexer of a semiconductor memory...
Integrated radiofrequency circuit component having a trimming diode
controlled by a trimming voltage provided...
An integrated component for radiofrequency applications has a resonant circuit with tuning diodes and trimming diodes that are connected in parallel. A...
Oscillator/mixer circuit having reduced area requirement when produced on a
An oscillator/mixer circuit having a reduced area requirement when producing it on a chip and where the circuit's mixer circuit is not based on the use of the...
Multistage differential amplifier with CMFB circuit
The invention relates to a multistage differential amplifier having an input stage, at which a differential input voltage is present, a load connected to the...
Semiconductor wafer testing system
A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die...
Alignment or overlay marks for semiconductor processing
An alignment or overlay mark with improved signal to noise ratio is disclosed. Improved signal-to-noise ratio results in greater depth of focus, thus improving...
Compliant relief wafer level packaging
A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant...
Interconnect arrangement and method for fabricating an interconnect
An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface...
Semiconductor structure and method for improving its ability to withstand
electrostatic discharge (ESD) and...
A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having...