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Patent # Description
US-6,914,841 System and method for refreshing a dynamic memory device
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a...
US-6,914,837 DRAM memory with a shared sense amplifier structure
A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as...
US-6,914,834 System and method for the functional testing of semiconductor memory chips
A system and a method for functionally testing fast semiconductor memory chips. The data shifting method proposed here is based on the fact that a low speed...
US-6,914,811 Method of driving one-time operable isolation elements and circuit for driving the isolation elements
A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation...
US-6,914,796 Semiconductor memory element with direct connection of the I/Os to the array logic
The invention relates to a semiconductor memory element comprising a plurality of data pins and at least two memory cell arrays, each of which comprises a...
US-6,914,491 Controlling an oscillator or a phase-delay device in a phase-control circuit
In a phase control loop, an output signal which is used to control an oscillator in a PLL or a phase-delay device in a DLL is generated by means of a...
US-6,914,328 Electronic component with an insulating layer formed from fluorinated norbornene polymer and method for...
An electronic component and a method of producing it, with at least one insulating layer is encompassed by the invention. The insulating layer includes a polymer...
US-6,914,320 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof
An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is...
US-6,914,297 Configuration for generating a voltage sense signal in a power semiconductor component
The invention relates to a configuration for generating a low-voltage signal proportional to the high voltage present between the source and the drain of a power...
US-6,914,292 Floating gate field-effect transistor
A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically...
US-6,914,270 IGBT with PN insulation and production method
The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same...
US-6,913,990 Method of forming isolation dummy fill structures
A method of providing dummy fill structures to meet the strict requirements for planarizing MRAM (Magnetic Random Access Memory) and other semiconductor devices...
US-6,913,987 Method for fabricating self-aligned contact connections on buried bit lines
Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word...
US-6,913,983 Integrated circuit arrangement and method for the manufacture thereof
A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the...
US-6,913,954 Programmable fuse device
A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first...
US-6,913,187 Method and arrangement for providing Vias in printed circuit boards
A method of providing thermal vias in a printed circuit board that includes one or more layers of board material is disclosed. The vias provide for conducting...
US-6,912,681 Circuit cell for test pattern generation and test pattern compression
A circuit for test pattern generation compression of circuits with a built-in self-test function has a test data coupling circuit having a test data input for...
US-6,912,153 Non-volatile memory cell
A memory cell stores data permanently in a memory material that can assume a first, high-resistance state and a second, low-resistance state, that is in a...
US-6,911,930 Cell array with mismatch reduction
A cell array has a plurality of cell elements integrated in a wafer in a bidimensional cell matrix, wherein each integrated cell element comprises a mismatch...
US-6,911,866 Method and device for switch-on current limiting in push-pull amplifying power stages
The invention provides a method for amplification of analog push-pull signals (101a, 101b) by means of a push-pull amplifier output stage (100) which has a first...
US-6,911,732 Integrated circuit
An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external...
US-6,911,696 LDMOS transistor
A lateral double-diffused MOS transistor (LDMOS) has a body zone and additional body regions assigned to the body zone, thereby producing a "deep body." The deep...
US-6,911,693 MOS transistor device
In order to form a MOS transistor device with a particularly low on resistance with a good avalanche strength at the same time, it is proposed to define the...
US-6,911,687 Buried bit line-field isolation defined active semiconductor areas
Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors...
US-6,911,390 Fabrication method for an interconnect on a substrate
Method for fabricating an interconnect on a substrate. The method includes applying a mask on the substrate, patterning the mask, so that it has an opening...
US-6,911,368 Arrangement for preventing short-circuiting in a bipolar double-poly transistor and a method of fabricating...
In a bipolar double-poly transistor comprising a layer of base silicon (1') on a silicon substrate (2'), a first layer of silicon dioxide (3') on the base...
US-6,911,284 Photomask and method for manufacturing the photomask
A photomask for the manufacture of integrated semiconductor products has at least one first region with principal structures that correspond to structures on the...
US-6,911,059 Abrasive pad and process for the wet-chemical grinding of a substrate surface
An abrasive pad is suitable for the wet-chemical grinding of a substrate surface. The novel abrasive pad has a polymer matrix with a defined water-solubility....
US-6,910,163 Method and configuration for the output of bit error tables from semiconductor devices
A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the...
US-6,910,161 Device and method for reducing the number of addresses of faulty memory cells
A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word...
US-6,910,144 Method and configuration for generating a clock pulse in a data processing system having a number of data channels
A method and a configuration for generating a clock pulse in a data processing system having a number of independent, non-synchronous digital data channels, is...
US-6,909,933 Method, device, computer-readable memory and computer program element for the computer-aided monitoring and...
In the case of a method for the computer-aided monitoring and controlling of a manufacturing process of a plurality of physical objects, the physical objects are...
US-6,909,932 Method for wafer position data retrieval in semiconductor wafer manufacturing
Semiconductor products, especially semiconductor wafers, are processed according to a defined sequence of orders with the products arranged in a container....
US-6,909,660 Random access memory having driver for reduced leakage current
One embodiment of the present invention provides a random access memory (RAM) including an array of memory cells arrange in a plurality of rows and columns,...
US-6,909,657 Pseudostatic memory circuit
A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at...
US-6,909,642 Self trimming voltage generator
Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the...
US-6,909,612 Connection system
A connection system detachably and mechanically connects an electronic component to a holder. The connection system has at least one stop element that provides a...
US-6,909,394 Quantizer for a sigma delta modulator, and sigma delta modulator
The invention relates to a quantizer (1) for a sigma delta modulator (10) having at least one input stage (2), the quantizer quantizing an input signal (21)...
US-6,909,340 Bulk acoustic wave filter utilizing resonators with different aspect ratios
The invention relates to bulk acoustic wave filters including at least two bulk acoustic wave resonators. Each of these resonators includes at least one first...
US-6,909,294 Time recording device and a time recording method employing a semiconductor element
A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate....
US-6,909,268 Current-mode switching regulator
A current mode switching controller contains at least one controllable semiconductor switch, an impedance, a voltage divider, an external control circuit for...
US-6,909,153 Semiconductor structure having buried track conductors, and method for generating an electrical contact with...
A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect...
US-6,909,152 High density DRAM with reduced peripheral device area and method of manufacture
A dynamic random access memory (DRAM) structure having a distance less than 0.14 .mu.m between the contacts to silicon and the gate conductor is disclosed. In...
US-6,909,141 Method for producing a vertical semiconductor transistor component and vertical semiconductor transistor component
A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has...
US-6,909,139 One transistor flash memory cell
An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The...
US-6,908,844 Metallization arrangement for semiconductor structure and corresponding fabrication method
The present invention provides a metallization arrangement for a semiconductor structure (1) having a first substructure plane (M1), preferably a first...
US-6,908,841 Support structures for wirebond regions of contact pads over low modulus materials
A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low...
US-6,908,831 Method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling...
A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer...
US-6,908,806 Gate metal recess for oxidation protection and parasitic capacitance reduction
A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal...
US-6,908,775 Method for performing an alignment measurement of two patterns in different layers on a semiconductor wafer
In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of...
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