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Patent # Description
US-6,971,039 DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second...
A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides...
US-6,970,899 Calculating unit and method for subtracting
Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass...
US-6,970,589 Method for inspecting defects on a mask
The whole-area defect inspection of masks is made possible by interconnecting two otherwise independent defect inspection systems via a powerful bus system or...
US-6,970,558 Method and device for suppressing noise in telephone devices
Device and method for noise suppression in telephone equipment, in particular with hands-free equipment, having a level discriminator, an additional filter with...
US-6,970,395 Memory device and method of reading data from a memory device
A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The...
US-6,970,390 DRAM memory circuit with sense amplifiers
In a DRAM memory circuit, the sense amplifiers, for amplifying the differential voltage sensed between the cores of a bit line, in each case contain two...
US-6,970,389 Integrated memory
An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals...
US-6,970,046 Digital phase-locked loop
A digital phase-locked loop with a digitally controlled oscillator is disclosed. The phase difference between a reference phase and a phase derived from the...
US-6,970,016 Data processing circuit and method for transmitting data
Data processing circuit including a single rail bus having a single rail line, a dual rail bus having a first dual rail line for data bits and a second dual rail...
US-6,970,006 Apparatus for the automated testing, calibration and characterization of test adapters
The apparatus enables the automated testing, calibration and characterization of test adapters for semiconductor devices. A holder for the test adapter can be...
US-6,969,917 Electronic chip component with an integrated circuit and fabrication method
The invention relates to an electronic chip component and a method for fabricating the chip component with a semiconductor chip having an integrated circuit...
US-6,969,905 Leadframe for semiconductor chips and electronic devices and production methods for a leadframe and for...
A leadframe for semiconductor chips and electronic devices produced on the leadframe includes providing the leadframe with a basic substrate, on which are...
US-6,969,863 Arrangement for feeding or dissipating heat to/from a semiconductor substrate for the purpose of preparing or...
The arrangement comprises a hot or cool plate (12) that has a substantially planar surface for accommodating the semiconductor substrate and for transmitting...
US-6,969,265 Electrically connecting integrated circuits and transducers
Apparatus and methods of electrically connecting integrated circuits and transducers are described. In particular, a transducer includes a base mountable on a...
US-6,968,544 Method for transformation of interface definitions and intermediate format tables thereof
A method for converting interface definitions within a source code program into an intermediate format includes identifying with a computer system objects in a...
US-6,968,518 Method of resolving missing graphical symbols in computer-aided integrated circuit design
A system and method is presented for resolving missing graphical symbols in computer-aided design of integrated circuits during schematic migration. The system...
US-6,968,483 Circuit and method for testing a data memory
A data memory to be tested is connected to a processing unit. Data items to be stored are produced from a test pattern data item in the processing unit and are...
US-6,968,481 Method and device for adapting/tuning signal transit times on line systems or networks between integrated circuits
A method and a device adapt/tune signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine...
US-6,968,049 Transmission of charging signals on a data transmission path
An apparatus for transmitting charging signals on a data transmission path having a line impedance includes a driver device for setting a line voltage level that...
US-6,967,999 Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks
An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal...
US-6,967,893 Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory
An integrated synchronous memory has a register which can store a frequency-range information item regarding whether the memory is operated in a first or in a...
US-6,967,606 Loop filter for a continuous time sigma delta analog to digital converter
A loop filter for a continuous time sigma delta analog to digital converter which converts an analog input signal into a digital output signal, said loop filter...
US-6,967,370 Integrated semiconductor circuit having a multiplicity of memory cells
An integrated semiconductor circuit can have memory cells, which can be read by word lines and bit lines. Two mutually adjacent bit lines in each case are...
US-6,967,147 Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor
Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen...
US-6,967,133 Method for fabricating a semiconductor structure
The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor...
US-6,966,496 Chip module
The chip module comprises a semiconductor chip, which is fixed on a main side of a substrate of planar extent. A component, which is provided for taking up,...
US-6,965,910 Calculating unit and method for adding
A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder...
US-6,965,809 Method for characterizing and simulating a chemical mechanical polishing process
A method for characterizing and simulating a CMP process, in which a substrate to be polished, in particular a semiconductor wafer, is pressed onto a polishing...
US-6,965,660 Digital phase-locked loop
A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock...
US-6,965,535 Integrated semiconductor memory circuit and a method for operating the same
An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and...
US-6,965,534 Random access memory using precharge timers in test mode
Embodiments of the present invention are illustrated in a random access memory. In one embodiment, the random access memory includes memory banks and precharge...
US-6,965,336 Systems and methods of bidirectional communication across an isolation barrier
A bi-directional isolation scheme is described in which digital data, including clock information, may be communicated bi-directionally across a single isolation...
US-6,965,331 Conversion arrangement and method for converting a thermometer code
The invention relates to an arrangement for converting a binary input signal corresponding to an n-bit thermometer code into a binary output code different...
US-6,965,278 Amplifier circuit with active gain step circuit
An amplifier circuit comprises a main stage amplifier connected between a RF input and a RF output and at least one secondary stage amplifier, which is connected...
US-6,965,275 Method and apparatus for tuning a filter
A method and an apparatus for tuning a filter is provided wherein the filter has at least one adjustable element for adjusting at least one performance parameter...
US-6,965,258 Sample-and-hold with no-delay reset
An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase....
US-6,965,247 Semiconductor device for detecting and adjusting a threshold value variation
The present invention generally relates to a semiconductor device and more specifically to a semiconductor device for detecting and adjusting threshold voltage...
US-6,964,912 Method for fabricating a semiconductor structure
A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate...
US-6,964,378 Circuit for a focused ion beam (FIB) sensor
A circuit is enabled to capacitively drive a memory cell (erasing, programming, and reading) via a capacitance. The capacitance is additionally present and...
US-6,963,737 Circuit configuration for metering pulse recognition
A circuit configuration for metering pulse recognition includes an A/D converter that receives a signal containing metering pulses, and a digital comparator...
US-6,963,514 Method for testing an integrated semiconductor memory, and integrated semiconductor memory
An integrated semiconductor memory that can be tested includes a control circuit and a memory cell having a selection transistor. In a normal operating mode, the...
US-6,963,257 Coupled BAW resonator based duplexers
A duplexer comprising a transmit resonator device and a receive resonator device for filtering transmit and receive signals. The resonator device has a first BAW...
US-6,963,096 Semiconductor element having a semi-magnetic contact
The invention relates to a magnetoresistive semiconductor element, including a first contact and a second contact, and also a layer of a nonmagnetic...
US-6,962,294 Integrated circuit having an active shield
Integrated circuit having security-critical circuit components arranged in a lower plane, data lines arranged in an upper plane, situated at least in part above...
US-6,961,917 Method for activating fuse units in electronic circuit device
The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the...
US-6,961,882 Memory chip and apparatus for testing a memory chip
The present invention provides a memory chip (100) which can be operated in a normal mode and in a test mode (TM) and which has a device (102) for outputting...
US-6,961,880 Recording test information to identify memory cell errors
A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal,...
US-6,961,846 Data processing unit, microprocessor, and method for performing an instruction
The present invention relates to a data processing unit for executing instructions stored in a memory comprising a plurality of registers coupled with an...
US-6,961,273 RAM memory circuit having a plurality of banks and an auxiliary device for testing
One embodiment of the invention provides a RAM memory circuit having k.gtoreq.2 banks, each of which having a multiplicity of memory cells and a selection device...
US-6,960,930 Method and apparatus for determining the minimum or maximum switching activity of a digital circuit
In order when designing a digital circuit to be able to determine the minimum or maximum switching activity for estimating the power consumption it is determined...
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