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Patent # Description
US-6,918,778 Configuration, plug-in mount and contact element for fixing and contacting switching assemblies on a substrate
Contact elements of a plug-in mount are connected in an electrically conducting manner to conductive contact zones on a surface of a substrate after the plug-in...
US-6,918,535 Security paper, method and device for checking the authenticity of documents recorded thereon
A safety paper with an embedded electronic circuit (1, 4, 7) is used to create more effective forgery-proof securities such as bank notes. In order to check...
US-6,917,563 Integrated memory
An integrated memory contains an access controller for controlling an access for the purpose of reading data from, or writing data to, a memory cell array. The...
US-6,917,562 Semi-conductor component with clock relaying device
The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK,...
US-6,917,549 Integrated memory and method for operating it
An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs...
US-6,917,234 Power switch arrangement and turn-off method therefor
The invention relates to a power switch arrangement having a semiconductor power switch connected by its load path serially in a load circuit, and a clamping...
US-6,917,214 Method for testing a plurality of devices disposed on a wafer and connected by a common data line
In a method for testing a plurality of devices, which are arranged on a wafer and connected to a common data line, wherein the devices are connectable to a test...
US-6,917,208 Method and test structure for determining resistances at a plurality of interconnected resistors in an...
A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are...
US-6,917,100 Circuit module having interleaved groups of circuit chips
A circuit module has a carrier (10) and multiple stacks of circuit chips arranged on a surface of the carrier. Each stack has multiple circuit chips arranged in...
US-6,917,055 Optoelectronic component and method for producing an optoelectronic component
An optoelectronic component has at least one light source which is monolithically integrated in a semiconductor material, in particular having a laser diode. At...
US-6,916,729 Salicide formation method
A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a...
US-6,916,721 Method for fabricating a trench capacitor with an insulation collar
A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried...
US-6,916,704 Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor
An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being...
US-6,916,185 Connection of integrated circuit to a substrate
The present invention provides a method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. Connecting occurs by...
US-6,915,945 Method for contact-connecting an electrical component to a substrate having a conductor structure
For the purpose of contact-connecting an electrical component, in particular a semiconductor component, on a substrate having a conductor structure, a joining...
US-6,914,851 Circuit element with timing control
A circuit element has an input for receiving an external clock with a clock period duration. A unit is provided to present the circuit element with information...
US-6,914,844 Deep power down switch for memory device
A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor...
US-6,914,841 System and method for refreshing a dynamic memory device
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a...
US-6,914,837 DRAM memory with a shared sense amplifier structure
A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as...
US-6,914,834 System and method for the functional testing of semiconductor memory chips
A system and a method for functionally testing fast semiconductor memory chips. The data shifting method proposed here is based on the fact that a low speed...
US-6,914,811 Method of driving one-time operable isolation elements and circuit for driving the isolation elements
A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation...
US-6,914,796 Semiconductor memory element with direct connection of the I/Os to the array logic
The invention relates to a semiconductor memory element comprising a plurality of data pins and at least two memory cell arrays, each of which comprises a...
US-6,914,491 Controlling an oscillator or a phase-delay device in a phase-control circuit
In a phase control loop, an output signal which is used to control an oscillator in a PLL or a phase-delay device in a DLL is generated by means of a...
US-6,914,328 Electronic component with an insulating layer formed from fluorinated norbornene polymer and method for...
An electronic component and a method of producing it, with at least one insulating layer is encompassed by the invention. The insulating layer includes a polymer...
US-6,914,320 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof
An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is...
US-6,914,297 Configuration for generating a voltage sense signal in a power semiconductor component
The invention relates to a configuration for generating a low-voltage signal proportional to the high voltage present between the source and the drain of a power...
US-6,914,292 Floating gate field-effect transistor
A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically...
US-6,914,270 IGBT with PN insulation and production method
The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same...
US-6,913,990 Method of forming isolation dummy fill structures
A method of providing dummy fill structures to meet the strict requirements for planarizing MRAM (Magnetic Random Access Memory) and other semiconductor devices...
US-6,913,987 Method for fabricating self-aligned contact connections on buried bit lines
Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word...
US-6,913,983 Integrated circuit arrangement and method for the manufacture thereof
A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the...
US-6,913,954 Programmable fuse device
A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first...
US-6,913,187 Method and arrangement for providing Vias in printed circuit boards
A method of providing thermal vias in a printed circuit board that includes one or more layers of board material is disclosed. The vias provide for conducting...
US-6,912,681 Circuit cell for test pattern generation and test pattern compression
A circuit for test pattern generation compression of circuits with a built-in self-test function has a test data coupling circuit having a test data input for...
US-6,912,153 Non-volatile memory cell
A memory cell stores data permanently in a memory material that can assume a first, high-resistance state and a second, low-resistance state, that is in a...
US-6,911,930 Cell array with mismatch reduction
A cell array has a plurality of cell elements integrated in a wafer in a bidimensional cell matrix, wherein each integrated cell element comprises a mismatch...
US-6,911,866 Method and device for switch-on current limiting in push-pull amplifying power stages
The invention provides a method for amplification of analog push-pull signals (101a, 101b) by means of a push-pull amplifier output stage (100) which has a first...
US-6,911,732 Integrated circuit
An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external...
US-6,911,696 LDMOS transistor
A lateral double-diffused MOS transistor (LDMOS) has a body zone and additional body regions assigned to the body zone, thereby producing a "deep body." The deep...
US-6,911,693 MOS transistor device
In order to form a MOS transistor device with a particularly low on resistance with a good avalanche strength at the same time, it is proposed to define the...
US-6,911,687 Buried bit line-field isolation defined active semiconductor areas
Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors...
US-6,911,390 Fabrication method for an interconnect on a substrate
Method for fabricating an interconnect on a substrate. The method includes applying a mask on the substrate, patterning the mask, so that it has an opening...
US-6,911,368 Arrangement for preventing short-circuiting in a bipolar double-poly transistor and a method of fabricating...
In a bipolar double-poly transistor comprising a layer of base silicon (1') on a silicon substrate (2'), a first layer of silicon dioxide (3') on the base...
US-6,911,284 Photomask and method for manufacturing the photomask
A photomask for the manufacture of integrated semiconductor products has at least one first region with principal structures that correspond to structures on the...
US-6,911,059 Abrasive pad and process for the wet-chemical grinding of a substrate surface
An abrasive pad is suitable for the wet-chemical grinding of a substrate surface. The novel abrasive pad has a polymer matrix with a defined water-solubility....
US-6,910,163 Method and configuration for the output of bit error tables from semiconductor devices
A method and a configuration for the output of bit error tables from semiconductor devices are described. A test control unit reads the bit error table from the...
US-6,910,161 Device and method for reducing the number of addresses of faulty memory cells
A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word...
US-6,910,144 Method and configuration for generating a clock pulse in a data processing system having a number of data channels
A method and a configuration for generating a clock pulse in a data processing system having a number of independent, non-synchronous digital data channels, is...
US-6,909,933 Method, device, computer-readable memory and computer program element for the computer-aided monitoring and...
In the case of a method for the computer-aided monitoring and controlling of a manufacturing process of a plurality of physical objects, the physical objects are...
US-6,909,932 Method for wafer position data retrieval in semiconductor wafer manufacturing
Semiconductor products, especially semiconductor wafers, are processed according to a defined sequence of orders with the products arranged in a container....
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