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Patent # Description
US-6,965,660 Digital phase-locked loop
A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock...
US-6,965,535 Integrated semiconductor memory circuit and a method for operating the same
An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and...
US-6,965,534 Random access memory using precharge timers in test mode
Embodiments of the present invention are illustrated in a random access memory. In one embodiment, the random access memory includes memory banks and precharge...
US-6,965,336 Systems and methods of bidirectional communication across an isolation barrier
A bi-directional isolation scheme is described in which digital data, including clock information, may be communicated bi-directionally across a single isolation...
US-6,965,331 Conversion arrangement and method for converting a thermometer code
The invention relates to an arrangement for converting a binary input signal corresponding to an n-bit thermometer code into a binary output code different...
US-6,965,278 Amplifier circuit with active gain step circuit
An amplifier circuit comprises a main stage amplifier connected between a RF input and a RF output and at least one secondary stage amplifier, which is connected...
US-6,965,275 Method and apparatus for tuning a filter
A method and an apparatus for tuning a filter is provided wherein the filter has at least one adjustable element for adjusting at least one performance parameter...
US-6,965,258 Sample-and-hold with no-delay reset
An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase....
US-6,965,247 Semiconductor device for detecting and adjusting a threshold value variation
The present invention generally relates to a semiconductor device and more specifically to a semiconductor device for detecting and adjusting threshold voltage...
US-6,964,912 Method for fabricating a semiconductor structure
A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate...
US-6,964,378 Circuit for a focused ion beam (FIB) sensor
A circuit is enabled to capacitively drive a memory cell (erasing, programming, and reading) via a capacitance. The capacitance is additionally present and...
US-6,963,737 Circuit configuration for metering pulse recognition
A circuit configuration for metering pulse recognition includes an A/D converter that receives a signal containing metering pulses, and a digital comparator...
US-6,963,514 Method for testing an integrated semiconductor memory, and integrated semiconductor memory
An integrated semiconductor memory that can be tested includes a control circuit and a memory cell having a selection transistor. In a normal operating mode, the...
US-6,963,257 Coupled BAW resonator based duplexers
A duplexer comprising a transmit resonator device and a receive resonator device for filtering transmit and receive signals. The resonator device has a first BAW...
US-6,963,096 Semiconductor element having a semi-magnetic contact
The invention relates to a magnetoresistive semiconductor element, including a first contact and a second contact, and also a layer of a nonmagnetic...
US-6,962,294 Integrated circuit having an active shield
Integrated circuit having security-critical circuit components arranged in a lower plane, data lines arranged in an upper plane, situated at least in part above...
US-6,961,917 Method for activating fuse units in electronic circuit device
The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the...
US-6,961,882 Memory chip and apparatus for testing a memory chip
The present invention provides a memory chip (100) which can be operated in a normal mode and in a test mode (TM) and which has a device (102) for outputting...
US-6,961,880 Recording test information to identify memory cell errors
A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal,...
US-6,961,846 Data processing unit, microprocessor, and method for performing an instruction
The present invention relates to a data processing unit for executing instructions stored in a memory comprising a plurality of registers coupled with an...
US-6,961,273 RAM memory circuit having a plurality of banks and an auxiliary device for testing
One embodiment of the invention provides a RAM memory circuit having k.gtoreq.2 banks, each of which having a multiplicity of memory cells and a selection device...
US-6,960,930 Method and apparatus for determining the minimum or maximum switching activity of a digital circuit
In order when designing a digital circuit to be able to determine the minimum or maximum switching activity for estimating the power consumption it is determined...
US-6,960,835 Stress-relief layer for semiconductor applications
In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a...
US-6,960,829 Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product
A semiconductor wafer is produced with an outer contact layer applied to the entire surface of an insulating layer and a rewiring layer embedded therein. At the...
US-6,960,798 High-voltage semiconductor component
A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode...
US-6,960,541 Process for fabrication of a semiconductor component having a tungsten oxide layer
A semiconductor element with at least one layer of tungsten oxide, optionally in a structured tungsten oxide layer, is described. The semiconductor element is...
US-6,960,532 Suppressing lithography at a wafer edge
Damage to the rim of a semiconductor wafer caused by etching processes is reduced by forming a rim of carbonized photoresist around the outer edge of the wafer,...
US-6,960,524 Method for production of a metallic or metal-containing layer
The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer,...
US-6,960,523 Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit...
An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a...
US-6,960,505 Method for manufacturing a multi-bit memory cell
A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge...
US-6,960,365 Vertical MIMCap manufacturing method
A method of manufacturing a vertical metal-insulator-metal capacitor (MIMCap) (10) in regions (19) of an insulating layer (14). Trenches for both conductive...
US-6,960,306 Low Cu percentages for reducing shorts in AlCu lines
In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal...
US-6,959,595 Method and device for monitoring the pressure in a tire
A tire pressure monitor and a method of measuring a pressure in a tire include a decision whether the tire pressure should be measured. The decision is made in...
US-6,958,626 Off chip driver
A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing...
US-6,958,613 Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit
Interface parameters for a plurality of semiconductor devices, particularly parameters for output drivers (i.e. on chip driver) and terminations (i.e. on die...
US-6,958,509 Integrated semiconductor product comprising a metal-insulator-metal capacitor
To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric...
US-6,958,501 Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure
A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact...
US-6,958,256 Process for the back-surface grinding of wafers
The present invention relates to a process for the back-surface grinding of wafers using films which have a support layer, which is known per se, and an adhesion...
US-6,957,581 Acoustic detection of mechanically induced circuit damage
An apparatus and method thereof includes at least one acoustic transducer for receiving acoustic emissions produced during a semiconductor fabrication process....
US-6,957,414 Method for determining the ability to project images of integrated semiconductor circuits onto alternating...
A method is used to check the direct convertibility of integrated semiconductor circuits into alternating phase masks. This is done by explicitly localizing the...
US-6,957,376 Turbo decoder and turbo decoding method
A turbo decoder for decoding a data signal transmitted via a disturbed channel has a symbol estimator and a digital signal processor. The symbol estimator...
US-6,957,373 Address generator for generating addresses for testing a circuit
An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for...
US-6,957,372 Repair of address-specific leakage
An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline...
US-6,956,946 Method and device for cryptographic processing with the aid of an elliptic curve on a computer
In the case of cryptographic processing with the aid of an elliptic curve, parameters of the elliptic curve are stored in a memory of a computer. These...
US-6,956,786 Random access memory with optional inaccessible memory cells
A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory...
US-6,956,782 Selective bank refresh
A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command...
US-6,956,409 Reference voltage detector for power-on sequence in a memory
System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The...
US-6,956,408 Drive device for a light-emitting component
A drive device for a light-emitting component including a reference source, which generates a current specification signal specifying a desired current through...
US-6,956,404 Driver circuit having a plurality of drivers for driving signals in parallel
In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a...
US-6,956,304 Integrated circuit and method for controlling a power supply thereof
Integrated circuit, which is supplied externally by a supply voltage, having at least one useful circuit and a power supply for the at least one useful circuit...
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