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Patent # Description
US-6,986,118 Method for controlling semiconductor chips and control apparatus
The invention relates to a method for operating semiconductor chips, particularly memory chips, which are arranged in groups on modules which are connected to a...
US-6,986,088 Method and apparatus for reducing the current consumption of an electronic circuit
The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic...
US-6,986,086 Method and device for simultaneous testing of a plurality of integrated circuits
An inventive device for simultaneous testing of a plurality of integrated circuits is described. Each integrated circuit of the plurality of integrated circuits...
US-6,986,079 Memory device method for operating a system containing a memory device for fault detection with two interrupt...
A method operates a system with a program-controlled unit. The program-controlled unit reads and executes data that are stored in a memory device and that...
US-6,985,993 Control register assembly
A control register assembly controls components to be controlled in an electric circuit. The control register assembly includes a control register. The control...
US-6,985,917 Configurable calculating unit
A calculating unit includes a first calculating unit block, a second calculating unit block, controller, and connector having connecting lines, wherein for each...
US-6,985,400 On-die detection of the system operation frequency in a DRAM to adjust DRAM operations
The present invention relates to a memory system including an external clock and a memory chip connected to the external clock. The external clock generates an...
US-6,985,398 Memory device having multiple array structure for increased bandwidth
One embodiment of the present invention provides a semiconductor memory including a bank of N memory arrays each having a corresponding array address, a bus...
US-6,985,390 Integrated memory circuit having a redundancy circuit and a method for replacing a memory area
An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy...
US-6,985,029 Circuit configuration for tolerance correction in a frequency demodulator
A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a...
US-6,984,578 Method for the production of an integrated circuit
The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one...
US-6,984,556 Method of forming an isolation layer and method of manufacturing a trench capacitor
A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF.sub.4/SiF.sub.4/O.sub.2...
US-6,984,555 Device and method for inhibiting oxidation of contact plugs in ferroelectric capacitor devices
A ferroelectric capacitor device and method for producing such a device comprises forming a substrate, and forming a contact plug passing through the substrate....
US-6,984,529 Fabrication process for a magnetic tunnel junction device
A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is...
US-6,984,446 Process for producing a metal layer on a substrate body, and substrate body having a metal layer
Process for producing a metal layer on a substrate body. The process includes applying conductive particles to a surface of the substrate body, so that the...
US-6,983,430 Method of resolving mismatched parameters in computer-aided integrated circuit design
A system and method for resolving mismatched parameters in computer-aided design of integrated circuits during schematic migration. The system compares the...
US-6,983,131 Circuit configuration for direct modulation
A circuit configuration for direction modulation contains an oscillator, whose output signal is split into quadrature components for modulation with a useful...
US-6,982,911 Memory device with common row interface
One embodiment of the present invention provides a semiconductor memory receiving an external address including an array address and a row address. The...
US-6,982,902 MRAM array having a segmented bit line
A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is...
US-6,982,893 Memory module having a plurality of integrated memory components
A memory module comprises a plurality of integrated memory components which are arranged on a carrier substrate. An access control circuit, which is arranged...
US-6,982,495 Mark configuration, wafer with at least one mark configuration, and a method of producing at least one mark...
A mark configuration for the alignment and/or determination of a relative position of at least two planes in relation to one another in a substrate and/or in...
US-6,982,202 Fabrication method for memory cell
Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is...
US-6,981,241 Method for eliminating phase conflict centers in alternating phase masks, and method for producing alternating...
In order to eliminate phase conflicts in alternating phase masks, the layout is modified after the phase conflicts have been localized. During the modification,...
US-6,981,175 Memory and method for employing a checksum for addresses of replaced storage elements
A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each...
US-6,981,127 Apparatus and method for aligning variable-width instructions with a prefetch buffer
A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined...
US-6,980,648 Telephone system with current regulation in the constant current region
A telephone system includes a transmission line for connection to at least one telephone and a telephone interface in communication with the transmission line....
US-6,980,607 Method for decoding a data signal
A turbo decoder is used in a method for blockwise decoding a data signal that is error protection coded at a transmitter and that is detected in a receiver. The...
US-6,980,304 Method for measuring a characteristic dimension of at least one pattern on a disc-shaped object in a measuring...
The measurement of the width of a pattern on a semiconductor wafer or a flat panel is carried out in an optical microscope or a scanning electron microscope in a...
US-6,980,139 Sigma-delta-modulator
A quantizer for a sigma delta modulator comprising at least one preliminary stage V1, V2), the quantizer quantizing an input signal (E.sub.Q) present at it in...
US-6,979,966 Method and device for detecting the motor position of an electric motor
A method and device for detecting the motor position of a DC motor includes evaluating the back-induced voltage of non-energized motor windings of the motor only...
US-6,979,887 Support matrix with bonding channel for integrated semiconductors, and method for producing it
Support matrices for semiconductors are often encapsulated in a region of the bonding leads, the so-called bonding channel. The encapsulation is effected using a...
US-6,979,853 DRAM memory cell and memory cell array with fast read/write access
The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be...
US-6,979,591 Connection of integrated circuits
A method for connecting a first integrated circuit having an elevated contact area lying on an elastic elevation on a main area thereof and a second integrated...
US-6,979,526 Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs
A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a...
US-6,979,522 Method for exposing at least one or at least two semiconductor wafers
A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g.,...
US-6,978,654 Scanning tip orientation adjustment method for atomic force microscopy
A method of calibrating an AFM scanner head of an AFM machine to determine the arc functions of the scanner head are provided. A method of measuring the actual...
US-6,978,405 Memory device with comparison units to check functionality of addressed memory cells
The memory device contains comparison units with which it is possible to check whether an address applied to the memory device is associated with a memory cell...
US-6,978,290 Carry ripple adder
A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for...
US-6,978,013 Device for establishing a galvanically separate connection between a telephone line and a signal processing...
A device for the DC-decoupled connection of a telephone line to a signal processing device at the subscriber end of the telephone line is disclosed. The device...
US-6,977,862 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a...
Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a...
US-6,977,831 Content addressable memory cell
One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is...
US-6,977,516 Semi-conductor component testing system with a reduced number of test channels
The invention involves a semi-conductor component testing system, a process for semi-conductor components, as well as an assembly, more particularly a wafer with...
US-6,977,427 Electronic component having stacked semiconductor chips in parallel, and a method for producing the component
An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in...
US-6,977,413 Bar-type field effect transistor and method for the production thereof
The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.
US-6,977,405 Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it
In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and,...
US-6,976,247 Generating an executable file
A method of generating an executable file includes subdividing a target name into portions at one or more predetermined points. The method also includes saving...
US-6,975,780 Electro-optical component
The invention relates to an electro-optical component with a millimeter or submillimeter antenna and an optical receiver. In order, in the case of such an...
US-6,975,779 Method for modifying the image size of video images
The invention relates to a method for changing the image size of video images, in which a decimation of video image signals (V) by an integral decimation factor...
US-6,975,550 Array transistor amplification method and apparatus for dynamic random access memory
As disclosed herein, a method and apparatus are provided for amplifying a signal by a transistor of an array of transistors that includes a storage cell...
US-6,975,536 Mass storage array and methods for operation thereof
Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual...
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