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Patent # Description
US-6,981,127 Apparatus and method for aligning variable-width instructions with a prefetch buffer
A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined...
US-6,980,648 Telephone system with current regulation in the constant current region
A telephone system includes a transmission line for connection to at least one telephone and a telephone interface in communication with the transmission line....
US-6,980,607 Method for decoding a data signal
A turbo decoder is used in a method for blockwise decoding a data signal that is error protection coded at a transmitter and that is detected in a receiver. The...
US-6,980,304 Method for measuring a characteristic dimension of at least one pattern on a disc-shaped object in a measuring...
The measurement of the width of a pattern on a semiconductor wafer or a flat panel is carried out in an optical microscope or a scanning electron microscope in a...
US-6,980,139 Sigma-delta-modulator
A quantizer for a sigma delta modulator comprising at least one preliminary stage V1, V2), the quantizer quantizing an input signal (E.sub.Q) present at it in...
US-6,979,966 Method and device for detecting the motor position of an electric motor
A method and device for detecting the motor position of a DC motor includes evaluating the back-induced voltage of non-energized motor windings of the motor only...
US-6,979,887 Support matrix with bonding channel for integrated semiconductors, and method for producing it
Support matrices for semiconductors are often encapsulated in a region of the bonding leads, the so-called bonding channel. The encapsulation is effected using a...
US-6,979,853 DRAM memory cell and memory cell array with fast read/write access
The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be...
US-6,979,591 Connection of integrated circuits
A method for connecting a first integrated circuit having an elevated contact area lying on an elastic elevation on a main area thereof and a second integrated...
US-6,979,526 Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs
A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a...
US-6,979,522 Method for exposing at least one or at least two semiconductor wafers
A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g.,...
US-6,978,654 Scanning tip orientation adjustment method for atomic force microscopy
A method of calibrating an AFM scanner head of an AFM machine to determine the arc functions of the scanner head are provided. A method of measuring the actual...
US-6,978,405 Memory device with comparison units to check functionality of addressed memory cells
The memory device contains comparison units with which it is possible to check whether an address applied to the memory device is associated with a memory cell...
US-6,978,290 Carry ripple adder
A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for...
US-6,978,013 Device for establishing a galvanically separate connection between a telephone line and a signal processing...
A device for the DC-decoupled connection of a telephone line to a signal processing device at the subscriber end of the telephone line is disclosed. The device...
US-6,977,862 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a...
Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a...
US-6,977,831 Content addressable memory cell
One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is...
US-6,977,516 Semi-conductor component testing system with a reduced number of test channels
The invention involves a semi-conductor component testing system, a process for semi-conductor components, as well as an assembly, more particularly a wafer with...
US-6,977,427 Electronic component having stacked semiconductor chips in parallel, and a method for producing the component
An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in...
US-6,977,413 Bar-type field effect transistor and method for the production thereof
The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.
US-6,977,405 Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it
In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and,...
US-6,976,247 Generating an executable file
A method of generating an executable file includes subdividing a target name into portions at one or more predetermined points. The method also includes saving...
US-6,975,780 Electro-optical component
The invention relates to an electro-optical component with a millimeter or submillimeter antenna and an optical receiver. In order, in the case of such an...
US-6,975,779 Method for modifying the image size of video images
The invention relates to a method for changing the image size of video images, in which a decimation of video image signals (V) by an integral decimation factor...
US-6,975,550 Array transistor amplification method and apparatus for dynamic random access memory
As disclosed herein, a method and apparatus are provided for amplifying a signal by a transistor of an array of transistors that includes a storage cell...
US-6,975,536 Mass storage array and methods for operation thereof
Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual...
US-6,975,238 System and method for automatically-detecting soft errors in latches of an integrated circuit
A circuit and method for detecting soft errors produced in latches. An exemplary embodiment of a circuit includes a block of concatenated latches, each latch...
US-6,975,183 BAW resonator having piezoelectric layers oriented in opposed directions
A BAW resonator includes a first piezoelectric layer made of a material oriented toward a first direction, and a second piezoelectric layer made of a material...
US-6,975,141 LVDS driver for small supply voltages
The invention relates to an LVDS driver for small supply voltages, particularly of less than 2.0 V, for producing a differential output signal (Pout, Nout),...
US-6,975,131 Integrated module having a delay element
Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving...
US-6,975,100 Circuit arrangement for regulating the duty cycle of electrical signal
A circuit arrangement for regulating the duty cycle of an electrical signal including a first input differential amplifier, to which an input signal is applied;...
US-6,975,004 Semiconductor component with optimized current density
A cellularly constructed semiconductor component has a connection electrode, which contact-connects some of the cells, and a connection line, which...
US-6,974,770 Self-aligned mask to reduce cell layout area
Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be...
US-6,974,743 Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates
Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an...
US-6,974,655 Silicon resist for photolithography at short exposure wavelengths and process for making photoresists
A chemically amplified photo-resist includes a polymer containing acid-labile radicals attached to a polar group and also contains anchor groups that allow...
US-6,974,339 Connector
A connector has a connector body, at least one contact and at least one bimetal stripe. One end of the contact is fixed to the connector body and another end of...
US-6,973,717 Method for producing a semiconductor device in chip format
A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is...
US-6,973,295 Determination of a differential offset in a radio device and radio device
A device for determining an offset value for an offset occurring in a differential transmission signal section of a radio device utilizes, for the purpose of...
US-6,973,293 Apparatus and method for compensating for the offset of a mixer
An apparatus and a method compare the output signal of a mixer in a detector with one of two input signals of the mixer, in order to compensate for the offset of...
US-6,973,248 Planar optical component, and a coupling device for coupling light between a planar optical component and an...
A multilayer planar optical component has a multiplicity of optical conductors. Each optical conductor is assigned a deflecting device that launches or couples...
US-6,973,205 Scratch-resistant coating for a semiconductor component
To increase the scratch resistance of a surface passivation, in particular, for fingerprint sensors, a antifrictional layer is applied to reduce the shearing...
US-6,973,181 Method of generating a ring signal in a subscriber line interface circuit technical field
In a method and a device for controlling the magnitude of the generated ring signal in a the Subscriber Line Interface Circuit (SLIC) the voltage of the A and B...
US-6,973,110 Monolithic laser configuration
A monolithic laser configuration has a substrate, a laser diode disposed on the substrate for generating a light beam, a photodetector disposed on the substrate...
US-6,973,008 Apparatus for flexible deactivation of word lines of dynamic memory modules and method therefor
An apparatus and a method are proposed, which can be used to delay a deactivation of a row address in the event of repeated access to a bank of an RLDRAM memory...
US-6,972,983 Increasing the read signal in ferroelectric memories
Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example,...
US-6,972,981 Semiconductor memory module
The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command...
US-6,972,832 Method of grounding a photoblank to a holding device
A retaining device for photo blanks, comprising a retaining member (1) with a supporting surface (3) for a photo blank (4) and a ground element (10) which can be...
US-6,972,701 A/D converter calibration
A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means...
US-6,972,641 FBAR ladder filter and method of grounding of FBAR ladder filters
A FBAR ladder filter which may yield less degradation in the stopband near the passband edges than conventionally grounded FBAR ladder filters. For that purpose...
US-6,972,613 Fuse latch circuit with non-disruptive re-interrogation
Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the...
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