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Patent # Description
US-7,010,672 Digital processor with programmable breakpoint/watchpoint trigger generation circuit
A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or...
US-7,010,619 CAN module with jointly utilized components for connecting to multiple CAN buses
A CAN module contains several sets of storage elements for storing several sets of data representing different states of components of the CAN module. For...
US-7,010,120 Method for adjusting a ringing signal current in a subscriber line and circuit arrangement
The invention creates a method for adjusting a ringing signal current in a subscriber line (106), a ringing signal generator (114) which generates the ringing...
US-7,010,063 Receiver circuit and method of processing a received signal
A receiver circuit of a cordless communication system has an analog signal processing section with a channel selection filter and a digital signal processing...
US-7,010,061 Configurable all-digital coherent demodulator system for spread spectrum applications
A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an...
US-7,010,000 Method and apparatus of determining properties of a signal transmission channel
The invention generally relates to a modem connected via a digital interface to a switched public telephone network and to a method for probing the line...
US-7,009,908 Decoding device
A decoding device includes a final decoder having at least one field-controlled semiconductor switching device. A transmission signal has a characteristic curve...
US-7,009,904 Back-bias voltage generator with temperature control
Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The...
US-7,009,902 Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a...
Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage...
US-7,009,900 Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise...
US-7,009,869 Dynamic memory cell
A dynamic memory cell which can be selected by means of a selection signal and the content of which can be read out by means of a bit line pair with a first and...
US-7,009,848 Method, adapter card and configuration for an installation of memory modules
Memory modules without signal-conditioning devices (unbuffered, unregistered) are provided in a system by using adapter cards that have signal-conditioning...
US-7,009,449 Adjustable gain amplifier arrangement with relaxed manufacturing constraints
An amplifier arrangement includes a variable-gain signal amplifier. A control block is used to process a control signal in order to set the gain. A trimming unit...
US-7,009,420 Input circuit for receiving a signal at an input on an integrated circuit
An input circuit for receiving a signal at an input on an integrated circuit, particularly a DRAM circuit, and for assessing the signal with respect to a...
US-7,009,417 Semiconductor module and methods for functionally testing and configuring a semiconductor module
A semiconductor module has a plurality of contact terminals used for external data interchange, address interchange and/or command interchange during normal...
US-7,009,404 Method and device for testing the ESD resistance of a semiconductor component
To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct...
US-7,009,403 Circuit arrangement for controlling and detecting the load current through a load
Circuit arrangement for controlling the current flow through a load in the case of detection of the current flow according to the current sense principle. The...
US-7,009,288 Semiconductor component with electromagnetic shielding device
A semiconductor component with an electromagnetic shielding device against alpha radiation, beta radiation and high-frequency electromagnetic radiation is...
US-7,009,263 Field-effect transistor
A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor...
US-7,009,230 Barrier stack with improved barrier properties
An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O.sub.2 is disclosed. The barrier stack is particularly useful in capacitor...
US-7,009,193 Utilization of an ion gauge in the process chamber of a semiconductor ion implanter
A device to implant impurities into a semiconductor wafer has a process chamber having a wall, a pressure compensation unit, a disk to support a plurality of...
US-7,008,853 Method and system for fabricating free-standing nanostructures
Systems and methods include introducing a semiconductor wafer into a process chamber. An etching chemistry is injected into the process chamber to etch a...
US-7,008,851 Silicon-germanium mesa transistor
A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk...
US-7,008,849 Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts
A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an...
US-7,008,836 Method to provide a triple well in an epitaxially based CMOS or BiCMOS process
A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.
US-7,008,493 Method for applying a semiconductor chip to a carrier element
A method is described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like consistency is...
US-7,007,260 Method for fabricating an integrated semiconductor circuit
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing...
US-7,007,164 Method and array for authenticating a first instance and a second instance
In order to authenticate a first entity at a second entity, a first number is generated by way of an asymmetric cryptographic method. This first number is...
US-7,006,560 Digital modem
Digital modem for data exchange between a data distribution unit (2) and at least one receiver (3, 4) which can be connected to the digital modem (1) with: a...
US-7,006,340 Circuit configuration for protecting a battery against deep discharge
The inventive circuit configuration has only two poles and is connected in series between the battery and the load. The circuit configuration interrupts the...
US-7,005,904 Duty cycle correction
A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty...
US-7,005,895 Driver circuit with frequency-dependent signal feedback
Driver circuit for driving a useful signal having: (a) at least one amplifier circuit (3a, 3b) with low output impedance for the signal amplification of the...
US-7,005,894 Adaptive voltage monitoring
A voltage monitoring arrangement including a number of comparison devices, which corresponds to a prescribed number of voltage ranges, compares the value of an...
US-7,005,882 Method and apparatus for determining the switching state of a transistor
A method for determining the switching state of a transistor having an insulated drive electrode. The drive electrode is charged during a switch-on cycle...
US-7,005,761 Circuit configuration for off-load switching, switch mode power supply, clocked supply, voltage regulator, lamp...
A circuit configuration is used for off-load switching. The circuit configuration can be used as a component in a switch mode power supply, a clocked supply, a...
US-7,005,723 Bipolar transistor and method of producing same
In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base...
US-7,005,640 Method and apparatus for the characterization of a depth structure in a substrate
The present invention provides a method for the characterization of a depth structure in a substrate at a surface of the substrate, in which a cutout is produced...
US-7,005,385 Method for removing a resist mask with high selectivity to a carbon hard mask used for semiconductor structuring
The present invention relates to a method for removing a resist selective to a carbon hard mask including providing an etching plasma comprising of at least...
US-7,005,360 Method for fabricating a microelectronic circuit including applying metal over and thickening the integrated...
A method for fabricating a microelectronic circuit having an improved electrically conductive element. The method includes providing a finished processed...
US-7,005,355 Method for fabricating semiconductor memories with charge trapping memory cells
A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer,...
US-7,005,351 Method for fabricating a transistor configuration including trench transistor cells having a field electrode,...
A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench...
US-7,005,346 Method for producing a memory cell of a memory cell field in a semiconductor memory
A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a...
US-7,005,337 Method for a parallel production of an MOS transistor and a bipolar transistor
The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of...
US-7,005,333 Transistor with silicon and carbon layer in the channel region
A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the...
US-7,005,240 Method for forming a hard mask in a layer on a planar device
A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in...
US-7,005,220 Method for structuring a lithography mask
A method for structuring a lithograph mask by forming a cured, electrically-conductive layer on a mask structure having a radiation-transmissive substrate and a...
US-7,003,432 Method of and system for analyzing cells of a memory device
A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated...
US-7,003,422 Method for connecting test bench elements and shell device
The invention provides a method for connecting test bench elements (102a 102f), and a shell device, a test bench element shell (201) partially or completely...
US-7,003,029 Method and device for equalizing and decoding a data signal
A method for equalizing and decoding an error-protected data signal transmitted via a radio channel is described. According to the method, an equalized data...
US-7,003,015 Apparatus and method for configurable multi-dwell search engine for spread spectrum applications
This invention provides a configurable multi-dwell search engine for performing automated efficient searches of a known code sequence space. Inputs from a...
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