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Patent # Description
US-7,052,820 Silicon-containing resist for photolithography
A photoresist includes a polymer having a main chain composed of alternating silicon and oxygen atoms and a polymer chain segment which linked as a side chain to...
US-7,052,808 Transmission mask with differential attenuation to improve ISO-dense proximity
An apparatus, system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a...
US-7,052,621 Bilayered metal hardmasks for use in Dual Damascene etch schemes
A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent...
US-7,051,253 Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment
According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test...
US-7,051,237 Program-controlled unit
A program-controlled unit has debug resources that outputs trace information including selected addresses, data and/or control signals and that can be used to...
US-7,050,826 Hardware structure for a transmission/reception device for mobile radio applications, and method for processing...
A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P1, P2, P3) and a processor...
US-7,050,763 Method and device for transferring a signal from a signal source to a signal sink in a system
The system has at least two electronic units between which signals are transferred from a first electronic unit and a second electronic unit. The first...
US-7,050,584 Method and system for regenerating a private key for a predetermined asymmetric cryptographic key pair
After a key pair with a public key and a corresponding private key has been determined on the basis of an initial value, the initial value is made available to a...
US-7,050,487 Method and circuit arrangement for determination of transmission parameters
The invention relates to a method and an apparatus for determination of parameters for a transmission path in a telecommunications system by a ...
US-7,050,340 Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor...
A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller...
US-7,050,073 Method and apparatus for scrolling an image to be presented on a display unit
In order to enable the gentlest possible scrolling of an image to be presented on a display unit, without restricting the scrolling range and with a low outlay,...
US-7,049,930 Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor...
An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, as well as to a semiconductor device including at...
US-7,049,884 Demodulation arrangement for a radio signal
A demodulation arrangement for a radio signal is disclosed wherein an I/Q mixer converts the radio signal to a real and an imaginary component and supplies the...
US-7,049,877 Switched level-shift circuit
Switched level-shift circuit (SLSC) for a signal-switch (1) which is provided for switching an applied analog input signal (V.sub.AIN), wherein the switched...
US-7,049,871 D-type flip-flop with a reduced number of transistors
A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback...
US-7,049,854 sense amplifier having low-voltage threshold transistors
The invention provides a sense amplifier apparatus (100) for bit line signals (103, 104) having a bit line pair which comprises two bit lines (107, 108) to which...
US-7,049,832 Circuit arrangement and method for determining the load current through an inductive load connected to a supply...
Circuit arrangement for determining the load current through an inductive load (L) connected to a supply voltage (Vbat) in a clocked manner includes a current...
US-7,049,669 LDMOS transistor
A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first...
US-7,049,656 Field-effect-controllable semiconductor configuration with a laterally extending channel zone
A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first...
US-7,049,651 Charge-trapping memory device including high permittivity strips
The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are...
US-7,049,647 Semiconductor memory cell with trench capacitor and selection transistor and method for fabricating it
A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor...
US-7,049,628 Semiconductor memory cell and semiconductor memory device
The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode...
US-7,049,241 Method for forming a trench in a layer or a layer stack on a semiconductor wafer
Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer...
US-7,049,228 Method for introducing structures which have different dimensions into a substrate
A process for introducing structures that have different dimensions, particularly with regard to depth, in which just one lithography level is required, is...
US-7,049,193 Maskless middle-of-line liner deposition
A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes...
US-7,048,450 Optoelectronic module with transmitter chip and connecting piece for the module with respect to an optical...
An optoelectronic module and a connecting piece for the module with respect to an optical fiber and with respect to a circuit board can have a semiconductor chip...
US-7,047,454 Integrated circuit having a data processing unit and a buffer memory
An integrated circuit includes a data processing unit, a buffer memory, and a setting memory. The buffer memory performs the function of registers for storing...
US-7,047,371 Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration...
An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In...
US-7,047,334 Device for supplying control signals to memory units, and a memory unit adapted thereto
A device for supplying control signals to memory units of a memory module comprises a first bus section for supplying a first part of the control signals to a...
US-7,047,155 Bus interface
A bus interface connects a device to a bus that connects a plurality of devices to one another. The bus interface described is distinguished in that a timer...
US-7,046,797 Telephone system with controllable ringing voltage
A telephone system includes a controllable ringing generator for generating a ringing signal and an interface for providing a ringing voltage derived from that...
US-7,046,564 Semiconductor memory
The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and...
US-7,046,363 Optical measurement system and method
An apparatus and method for measuring feature sizes having form birefringence. The method includes providing a surface having surface features thereon; radiating...
US-7,046,178 Method and device for the calibration of a weighted network
Improved methods for the calibration, in particular for self-calibration, of an A/D or D/A converter with weighted network (CN) are proposed. Only a relevant...
US-7,046,081 Amplifier circuit with passive gain step circuit
An amplifier circuit includes an amplifier connected between an HF input and HF output and a coupling circuit connected in parallel to the amplifier between the...
US-7,046,060 Method and apparatus compensating for frequency drift in a delay locked loop
A delay locked loop (DLL) according to the present invention includes a cycle time detector to determine the quantity of delay elements within a clock cycle and...
US-7,045,881 Electronic component with shielding and method for its production
An electronic component with shielding is described. The component has a semiconductor chip with a semiconductor substrate. Disposed in a region of a rear side...
US-7,045,855 Semiconductor device and corresponding fabrication method
A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first...
US-7,045,837 Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing
The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying...
US-7,045,422 Semiconductor gate structure and method for fabricating a semiconductor gate structure
A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least...
US-7,045,274 Process for structuring a photoresist by UV at less than 160 NM and then aromatic and/or alicyclic amplification
A process amplifies structured resists by utilizing a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an amplification...
US-7,045,273 Process for silylating photoresists in the UV range
A process for the amplification of structured resists utilizes a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an...
US-7,045,254 Mask with programmed defects and method for the fabrication thereof
A mask, and in particular a phase shift product mask, utilizes predetermined defects being produced during the fabrication thereof in the so-called "second...
US-7,045,070 Method of producing an electrode configuration and method of electrically contacting the electrode configuration
The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at...
US-7,043,653 Method and apparatus for synchronous signal transmission between at least two logic or memory components
An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the...
US-7,043,625 Method and apparatus for adding user-defined execution units to a processor using configurable long instruction...
The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to...
US-7,043,197 Telecommunication system for the bidirectional transmission of data and voice signals
Telecommunication system for bidirectional transmission of data and voice signals with a data network (2), which is connected via a satellite data transmission...
US-7,042,953 Method and arrangement for compensating signal echoes during duplex data transmission with discrete multitone...
A system and method for compensating for signal echoes during duplex data transmission with discrete multitone modulation includes determining, the error of a...
US-7,042,789 Energy storing memory circuit
The invention relates to a memory arrangement having an energy storage device (store) which collects the energy transported during the flowing of a write or read...
US-7,042,786 Memory with adjustable access time
A memory comprising a memory array, an address buffer configured to receive an external address, a refresh address counter configured to generate a refresh...
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