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Patent # Description
US-7,029,955 Optically and electrically programmable silicided polysilicon fuse device
A silicided polysilicon based fuse device that is programmable by optical and electrical energy in the polysilicon layer without damage to nearby structures,...
US-7,029,808 Photosensitive coating material for a substrate and process for exposing the coated substrate
A radiation-sensitive coating material, in addition to a base polymer, has a solvent and a radiation-active substance which forms an acid on irradiation by light...
US-7,028,399 Wiring process
The present invention provides a process for wiring electrical contact sites, in particular on the surface of an electronic or microelectronic component, with...
US-7,028,243 Method and device for error correction of data blocks
In a method for error correcting a data signal that is transmitted via a channel and contains data blocks with associated error checking information, the data...
US-7,028,234 Method of self-repairing dynamic random access memory
A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the...
US-7,027,943 Method, device, computer-readable storage medium and computer program element for the computer-aided monitoring...
In the case of the method for the computer-aided monitoring of process parameters of a manufacturing process of a physical object, object data which identify the...
US-7,027,625 Fingerprint sensor with potential modulation of the ESD protective grating
The invention relates to fingerprint sensors. A fingerprint sensor has a plurality of sensor electrodes below a surface intended for contacting the underside of...
US-7,027,592 Non-linear echo cancellation in discrete multi-tone systems
A circuit arrangement for two-wire/four-wire conversion in a DMT system, which is connected to a digital reception path, a digital transmission path and also an...
US-7,027,287 Storage capacitor with high memory capacity and low surface area
A storage capacitor includes at least one first electrode adjacent to at least one second electrode, whereby a lateral capacity is formed between these...
US-7,026,865 Analogue amplifier with multiplexing capability
An analogue amplifier with multiplexing capability, without the need to incorporate a multiplexor, comprising an input port, a test input port, an output port, a...
US-7,026,857 Multiplier circuit
A multiplier circuit includes a multiplier core with two cross-coupled transistor pairs. First and second signal sources are respectively driven by first and...
US-7,026,547 Semiconductor device and a method for fabricating a semiconductor device
A semiconductor device (10) includes a semiconductor component integrated in a semiconductor substrate and a conductive pad (110) arranged on top of the...
US-7,026,220 Method for production of charge-trapping memory devices
The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory...
US-7,025,615 Fabrication method, varactor, and integrated circuit
A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a...
US-7,025,278 Method for preventing illegitimate use of chip cards
In order to detect attempted interventions in the vicinity of a smart card, a sensor hierarchy is used. Abnormal operating states are first detected by less...
US-7,024,578 Array of synchronized memory modules
A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a...
US-7,024,570 Low-power indicator
A random access memory with a low power mode indicator. The random access memory includes a state machine for generating a power mode output signal. A power mode...
US-7,024,326 Method of optimizing the timing between signals
A method of optimizing the timing between signals to be latched and a respective latching clock signal is suggested wherein test timings are provided according...
US-7,023,985 Circuit for electronically generating a call impedance
The present invention relates to a circuit for electronically generating a call impedance in telephone terminals, comprising a call alternating voltage that may...
US-7,023,930 Reducing the crest factor of a multicarrier signal
A method for reducing the crest factor of a multi-carrier signal includes evaluating an inverse Fourier transform of the multi-carrier signal, thereby generating...
US-7,023,916 Method and device for estimating motion in a digitized image with pixels
A method and arrangement are provided for motion estimation in a digitized picture having pixels, the pixels being grouped into picture blocks. The pixels can be...
US-7,023,760 Memory arrangement for processing data, and method
The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control...
US-7,023,701 Device for cooling memory modules
A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further...
US-7,023,373 Multi-stage ADC with shared amplifier and reference voltage selection
The invention provides a clocked analog/digital converter for successive approximation which is designed using a jointly used amplifier and a dynamic range...
US-7,023,276 Differential amplifier circuit
A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control...
US-7,023,191 Voltage regulator with adjustable output impedance
The invention relates to a voltage regulator having an output terminal (AK) for the provision of an output voltage and connection of a load, an output capacitor...
US-7,023,184 DC-DC converter with stabilized output voltage
A DC-DC converter is provided with a series circuit formed by an inductor and a capacitor, an output voltage for a load being tapped off across the capacitor and...
US-7,023,097 FBGA arrangement
The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads...
US-7,023,086 Semiconductor component arrangement with a reduced oscillation tendency
The present invention relates to a circuit assembly with at least two semiconductor components, each having terminals, whereby at least one terminal of the first...
US-7,023,063 Arrangement of microstructures
A method referred to as a "cellular damascene method" utilizes a multiplicity of regularly arranged closed cavities referred to as "cells", which are produced in...
US-7,023,053 Differential transistor pair
A differential transistor pair comprises a plurality of transistor cells in a substrate. Each cell comprises first drain regions at the respective edge of the...
US-7,023,028 Protection structure for protection from electrostatic discharge and integrated circuit
An ESD protection structure for protecting an integrated circuit from electrostatic discharge, having a bipolar protection element, whose emitter is formed by an...
US-7,023,008 Resistive memory element
An electrically operated, resistive memory element includes a volume of resistive memory material, adapted to be switched between different detectable resistive...
US-7,022,917 Construction and electrical connection technique in textile structures
Method for electrically connecting an electrical conductor to an electronic component including the steps of providing a textile material in which at least one...
US-7,022,582 Microelectronic process and structure
The present invention relates to a process for integrating air as dielectric in semiconductor devices, comprising the steps of: a. applying a layer of a...
US-7,022,560 Method to manufacture high voltage MOS transistor by ion implantation
A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain...
US-7,022,549 Method for connecting an integrated circuit to a substrate and corresponding arrangement
An integrated circuit, in particular from a chip, a wafer or a hybrid, to a substrate. A package is provided for the integrated circuit, which has a connection...
US-7,022,209 PVD method and PVD apparatus
A PVD method and a PVD apparatus use a rotating magnetic field in order to increase the yield. The magnetic field is provided such that it essentially vanishes,...
US-7,020,806 Method for testing memory units to be tested and test device
The invention provides a method for testing a memory unit (113) to be tested in a test device (100), the memory unit (113) to be tested being introduced into the...
US-7,020,759 Device and method for associating information concerning memory cells of a memory with an external memory
In a device and a method associating information concerning first memory cells and second memory cells of a memory element with an external memory, with each...
US-7,020,730 Method for operating a microprocessor configuration and microprocessor configuration
A microprocessor configuration includes a central control and processing unit, a bus having a bus state line and data/address lines, and units connected to the...
US-7,020,229 Phase-locked loop
A phase-locked loop is described and has a phase detector that provides at its output per clock cycle a current pulse whose pulse duration is a measure of a...
US-7,020,149 Method for operating a switching system for data packets
A method for operating a switching system for data packets includes providing a switching system having inputs and outputs, temporarily storing data packets at...
US-7,019,981 Making contact with semiconductor chips in chip cards
A chip card having a chip card body, a semiconductor chip and a carrier substrate, the carrier substrate being provided on both sides with surface contacts and...
US-7,019,953 Voltage protection circuit
A voltage protection circuit for a terminal of an electronic device, for example the TIP and RING lines of a linecard, is provided. The voltage protection...
US-7,019,566 Bi-polar PNP chopper
A switch comprises an input with two input lines and an input stage comprising four current controlled PNP-transistors and four resistors, and an output...
US-7,019,554 Methods and apparatus for active termination of high-frequency signals
An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an...
US-7,019,384 Integrated, tunable capacitance device
An integrated, tunable capacitance device includes a semiconductor region, which is, preferably, N-doped, formed in a semiconductor body, having an insulating...
US-7,019,382 Arrangement for ESD protection of an integrated circuit
To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad...
US-7,019,305 Biosensor circuit and sensor array consisting of a plurality of said biosensor circuits and biosensor array
Biosensor circuit arrangement including a substrate, a sensor element formed in or on a surface region of the substrate with a physical parameter, which is...
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