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Patent # Description
US-7,015,092 Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts
Methods and devices that provide improved isolation and alignment of gate conductors or gate contacts of vertical transistors in deep trench memory cells. A...
US-7,015,049 Fence-free etching of iridium barrier having a steep taper angle
An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer...
US-7,013,412 Method for segmentally deinterleaving a data signal
In a method for deinterleaving a data signal interleaved in blocks in accordance with a prescribed interleaving specification, deinterleaving target addresses...
US-7,013,374 Integrated memory and method for setting the latency in the integrated memory
An integrated memory has address inputs for applying a row address or a column address and a latency value, and an instruction decoder with a signal input. The...
US-7,012,979 Tone signal detection circuit for detecting tone signals
Tone signal detection circuit for a receiving circuit for detecting at least one tone signal of predetermined tone signal frequency (f.sub.E) which is contained...
US-7,012,843 Device for driving a memory cell of a memory module by means of a charge store
A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (V.sub.EXT) and an operating frequency (f.sub.CLK),...
US-7,012,819 Method for operating a switching converter and drive circuit for driving a switch in a switching converter
The present invention relates to a method for operating a switching converter which has input terminals for the application of an input voltage, output terminals...
US-7,012,751 Semitransparent mirror and methods for producing and operating such a mirror
The invention relates to a semitransparent mirror and a method for producing and for operating the semitransparent mirror. The semitransparent mirror has a...
US-7,012,531 Product label, method of producing product labels and method for identifying products in a contactless and...
A product label includes a semiconductor chip and an antenna. The semiconductor chip stores information about a product. The antenna transmits the information...
US-7,012,468 Circuit configuration and method for reducing the 1/f noise of MOSFETs
The circuit configuration and the associated method allow reducing the 1/f noise of MOSFETs in an electronic circuit, especially in an integrated circuit with...
US-7,012,410 Regulating system
A regulating system comprises an input terminal for applying an input voltage, and an output terminal for providing an output voltage. A semiconductor element is...
US-7,012,313 MOS transistor in a single-transistor memory cell having a locally thickened gate oxide
A MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and a process for producing the transistor. The MOS transistor can be...
US-7,012,289 Memory cell having a thin insulation collar and memory module
A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a...
US-7,012,003 Memory for producing a memory component
The invention relates to a method for producing a memory component comprising a memory location (104) having memory cells and first control electrode strips...
US-7,011,986 Method for manufacturing a housing for a chip with a micromechanical structure
In a housing manufacturing method a base is provided with first contact elements with a photolithographically patternable layer that is patterned for exposing...
US-7,011,936 Photomask and method of structuring a photoresist by double exposure with imaging auxiliary structures and...
A method for structuring photoresists and a corresponding photolithography mask utilize a principal structure and an auxiliary structure. In addition to the...
US-7,011,909 Photolithography mask and method of fabricating a photolithography mask
A photolithography mask is based on a combination of a half-tone phase mask and an alternating phase mask such that, when the radiation passes through some of...
US-7,011,574 Polyelectrolyte dispensing polishing pad
A polyelectrolyte dispensing polishing pad, a process for its production and a method of polishing, e.g., chemical mechanical polishing (CMP), a substrate such...
US-7,010,672 Digital processor with programmable breakpoint/watchpoint trigger generation circuit
A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or...
US-7,010,619 CAN module with jointly utilized components for connecting to multiple CAN buses
A CAN module contains several sets of storage elements for storing several sets of data representing different states of components of the CAN module. For...
US-7,010,120 Method for adjusting a ringing signal current in a subscriber line and circuit arrangement
The invention creates a method for adjusting a ringing signal current in a subscriber line (106), a ringing signal generator (114) which generates the ringing...
US-7,010,063 Receiver circuit and method of processing a received signal
A receiver circuit of a cordless communication system has an analog signal processing section with a channel selection filter and a digital signal processing...
US-7,010,061 Configurable all-digital coherent demodulator system for spread spectrum applications
A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an...
US-7,010,000 Method and apparatus of determining properties of a signal transmission channel
The invention generally relates to a modem connected via a digital interface to a switched public telephone network and to a method for probing the line...
US-7,009,908 Decoding device
A decoding device includes a final decoder having at least one field-controlled semiconductor switching device. A transmission signal has a characteristic curve...
US-7,009,904 Back-bias voltage generator with temperature control
Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The...
US-7,009,902 Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a...
Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage...
US-7,009,900 Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise...
US-7,009,869 Dynamic memory cell
A dynamic memory cell which can be selected by means of a selection signal and the content of which can be read out by means of a bit line pair with a first and...
US-7,009,848 Method, adapter card and configuration for an installation of memory modules
Memory modules without signal-conditioning devices (unbuffered, unregistered) are provided in a system by using adapter cards that have signal-conditioning...
US-7,009,449 Adjustable gain amplifier arrangement with relaxed manufacturing constraints
An amplifier arrangement includes a variable-gain signal amplifier. A control block is used to process a control signal in order to set the gain. A trimming unit...
US-7,009,420 Input circuit for receiving a signal at an input on an integrated circuit
An input circuit for receiving a signal at an input on an integrated circuit, particularly a DRAM circuit, and for assessing the signal with respect to a...
US-7,009,417 Semiconductor module and methods for functionally testing and configuring a semiconductor module
A semiconductor module has a plurality of contact terminals used for external data interchange, address interchange and/or command interchange during normal...
US-7,009,404 Method and device for testing the ESD resistance of a semiconductor component
To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct...
US-7,009,403 Circuit arrangement for controlling and detecting the load current through a load
Circuit arrangement for controlling the current flow through a load in the case of detection of the current flow according to the current sense principle. The...
US-7,009,288 Semiconductor component with electromagnetic shielding device
A semiconductor component with an electromagnetic shielding device against alpha radiation, beta radiation and high-frequency electromagnetic radiation is...
US-7,009,263 Field-effect transistor
A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor...
US-7,009,230 Barrier stack with improved barrier properties
An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O.sub.2 is disclosed. The barrier stack is particularly useful in capacitor...
US-7,009,193 Utilization of an ion gauge in the process chamber of a semiconductor ion implanter
A device to implant impurities into a semiconductor wafer has a process chamber having a wall, a pressure compensation unit, a disk to support a plurality of...
US-7,008,853 Method and system for fabricating free-standing nanostructures
Systems and methods include introducing a semiconductor wafer into a process chamber. An etching chemistry is injected into the process chamber to etch a...
US-7,008,851 Silicon-germanium mesa transistor
A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk...
US-7,008,849 Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts
A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an...
US-7,008,836 Method to provide a triple well in an epitaxially based CMOS or BiCMOS process
A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.
US-7,008,493 Method for applying a semiconductor chip to a carrier element
A method is described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like consistency is...
US-7,007,260 Method for fabricating an integrated semiconductor circuit
A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing...
US-7,007,164 Method and array for authenticating a first instance and a second instance
In order to authenticate a first entity at a second entity, a first number is generated by way of an asymmetric cryptographic method. This first number is...
US-7,006,560 Digital modem
Digital modem for data exchange between a data distribution unit (2) and at least one receiver (3, 4) which can be connected to the digital modem (1) with: a...
US-7,006,340 Circuit configuration for protecting a battery against deep discharge
The inventive circuit configuration has only two poles and is connected in series between the battery and the load. The circuit configuration interrupts the...
US-7,005,904 Duty cycle correction
A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty...
US-7,005,895 Driver circuit with frequency-dependent signal feedback
Driver circuit for driving a useful signal having: (a) at least one amplifier circuit (3a, 3b) with low output impedance for the signal amplification of the...
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